Multi-Layer Epitaxial Source/Drain Contacts for Low-Resistance FETs
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in achieving low contact resistance in source/drain structures of FinFETs and GAA FETs, particularly due to the use of silicide layers, which are crucial for reducing resistance and enhancing device performance.
Innovation Solution
The formation of multi-layer epitaxial structures with different lattice constants, such as SiC, SiP, SiCP, Ge, and SixGe1-x, followed by the creation of silicide or germanide layers using transition metals like Ti, Ta, Ni, and Co, to form low-resistance contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicide layers are formed on source/drain structures to reduce contact resistance, then electrical conductivity is improved, but manufacturing complexity increases due to multi-layer epitaxial structures with different lattice constants
Solution Approach 1:
The source/drain structure is divided into multiple epitaxial layers with different lattice constants (e.g., SiGe layer and Si layer). Each layer serves a specific function: the SiGe layer provides stress management and low contact resistance, while the Si layer provides lattice matching with the channel. This segmentation allows optimization of contact resistance without compromising overall device performance.
Solution Approach 2:
The patent employs composite material structures by combining different semiconductor materials (SiGe and Si) with distinct lattice constants in a layered configuration. This composite approach enables simultaneous achievement of low contact resistance through SiGe and proper lattice matching through Si, resolving the contradiction between reliability improvement and structural complexity.
2Reliability
If multi-layer epitaxial structures with different lattice constants are used, then contact resistance is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent systematically varies the lattice constant parameter across different epitaxial layers. By carefully selecting and controlling the composition ratios (e.g., Ge concentration in SiGe), the lattice constants are adjusted to achieve optimal contact resistance while maintaining manufacturability. This parameter optimization reduces the stringency of manufacturing precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces contact resistance, thereby improving the performance and efficiency of semiconductor devices by ensuring better electrical conductivity and stress management in the channel regions.
Implementation Method 1
sources and drains are formed by using an epitaxial growth method
Data Source
AI summary
A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.