Epitaxial Source Drain Regions for Dislocation-Free Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The scaling down of semiconductor integrated circuits leads to challenges in forming source/drain regions with deep junction profiles and substantial damage from ion implantations, which can result in short-channel effects and transient-enhanced diffusion, while high thermal budget annealing may exacerbate these issues.
Innovation Solution
A method involving the epitaxial growth of a silicon-containing material with dopants in recessed regions near the gate electrodes, using a cyclic deposition and etching process to minimize dislocations and prevent gate corner defects, followed by a post-deposition etch to remove residual dislocations, ensuring the source/drain regions are free of defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If ion implantation is used to form source/drain regions with deep junction profiles, then dopant concentration is improved, but dislocation and damage are increased
Solution Approach 1:
The patent replaces the mechanical ion implantation process with a chemical epitaxial growth process. Instead of physically bombarding the substrate with ions to achieve dopant concentration, the method uses in-situ doped epitaxial growth where dopants are incorporated during the silicon layer formation. This substitution eliminates the mechanical damage and dislocations associated with ion implantation while achieving the desired deep junction profiles and dopant concentrations.
Solution Approach 2:
The patent changes the fundamental process parameters from ion implantation (high energy, mechanical) to epitaxial growth (low energy, chemical). By controlling growth temperature, pressure, and dopant gas flow during epitaxial growth, the method achieves deep junction profiles with high dopant activation without the harmful effects of ion implantation. The growth conditions are optimized to ensure proper dopant incorporation while maintaining crystal structure integrity.
2Reliability
If high thermal budget annealing is used to activate dopants, then dopant activation is improved, but short-channel effects and transient-enhanced diffusion are worsened
Solution Approach 1:
The patent substitutes thermal annealing with a low-energy epitaxial growth process for dopant activation. During in-situ doped epitaxial growth, dopants are incorporated into the crystal lattice as the silicon layer forms, achieving high activation levels without requiring high-temperature thermal processing. This eliminates the harmful transient-enhanced diffusion and short-channel effects that result from high thermal budget annealing.
Solution Approach 2:
The patent performs dopant incorporation during the epitaxial growth process itself, before any thermal annealing is required. By pre-incorporating dopants at controlled concentrations during growth, the method achieves sufficient activation without needing subsequent high-temperature annealing steps, thereby preventing the harmful effects of thermal processing on device characteristics.
3Productivity
If scaling down is implemented to increase functional density, then production efficiency is improved, but power dissipation is worsened
Solution Approach 1:
The patent changes the device architecture parameters by implementing strained silicon channels and optimized junction profiles through epitaxial growth. The strained silicon modifies carrier mobility and device characteristics, enabling higher functional density while maintaining lower power dissipation. The precise control of dopant profiles and junction depths achieved through epitaxial growth allows for optimized device performance that balances density and power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively forms source/drain regions with higher dopant activation levels and minimizes dislocation-related performance degradation, maintaining transistor performance and widening the process window for fabrication without gate corner defects.
Implementation Method 1
epitaxial growth of a silicon-containing material with dopants in recessed regions near the gate electrodes
Implementation Method 2
cyclic deposition and etching process to minimize dislocations and prevent gate corner defects, followed by a post-deposition etch to remove residual dislocations
Data Source
AI summary
An integrated circuit includes a gate structure disposed over a substrate. The integrated circuit further includes a silicon-containing material structure disposed over a recess adjacent to the gate structure. The silicon-containing material structure includes a first epitaxial layer and a second epitaxial layer. A gate corner of the gate structure is free of dislocation and a corner of the second epitaxial layer away from a surface of the substrate and next to a spacer of the gate structure includes dislocations, wherein the dislocations are away from the gate corner.