Epitaxial Source Drain Features for Logic Memory Device Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for forming raised source/drain features in semiconductor devices, such as MOSFETs, have limitations in enhancing carrier mobility and device performance, particularly in distinguishing between logic and memory device requirements.
Innovation Solution
The method involves forming epitaxial features with specific geometries and materials in source/drain regions, where epitaxial features in logic device regions are made taller and wider to provide stress and reduce contact resistance, while those in memory device regions are designed to be narrower to enhance device density, using techniques like cyclic deposition and etching to control growth orientation and doping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If epitaxial features are made taller and wider in logic device regions to provide stress and reduce contact resistance, then device performance is improved, but device density is reduced
Solution Approach 1:
The patent applies local quality by forming different epitaxial feature geometries in different device regions. Logic device regions receive taller and wider epitaxial features to maximize stress and reduce contact resistance, while memory device regions receive narrower epitaxial features to maintain high device density. This region-specific differentiation resolves the contradiction by optimizing each region for its specific functional requirements rather than using a uniform approach across the entire semiconductor device.
2Area of stationary object
If epitaxial features are made narrower in memory device regions to enhance device density, then device density is improved, but stress and carrier mobility enhancement are reduced
Solution Approach 1:
The patent implements local quality by tailoring epitaxial feature dimensions to the specific requirements of each device region. In memory device regions, narrower epitaxial features are formed to maximize device density, accepting reduced stress enhancement as a trade-off. Conversely, logic device regions receive wider epitaxial features to prioritize carrier mobility and device performance. This spatially differentiated approach resolves the contradiction by allowing each region to optimize for its primary function.
Solution Approach 2:
The patent employs parameter changes by varying the epitaxial growth conditions and feature dimensions based on device type. Different epitaxial growth parameters are used to control the height, width, and material composition of epitaxial features in logic versus memory regions. This parameter optimization allows the system to achieve acceptable carrier mobility in memory devices with narrower features while maintaining high device density, resolving the contradiction through controlled variation of physical and chemical parameters.
3Productivity
If scaling down process is used to increase functional density, then production efficiency is improved, but processing complexity is increased
Solution Approach 1:
The patent applies segmentation by dividing the semiconductor device into distinct logic device regions and memory device regions, each with optimized epitaxial feature characteristics. This regional segmentation allows different processing optimizations to be applied to different areas, managing the complexity of scaled-down processing by treating different functional blocks separately rather than attempting to optimize the entire device uniformly. The segmentation approach enables parallel processing streams with different parameters, reducing overall processing complexity while maintaining high functional density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the performance of logic devices by increasing stress and reducing contact resistance, while optimizing memory device density by controlling epitaxial feature profiles and doping, thus addressing the specific needs of both device types.
Implementation Method 1
strained source/drain features (e.g., stressor regions) have been implemented using epitaxial (epi) semiconductor materials to enhance carrier mobility and improve device performance. Forming a MOSFET with stressor regions often epitaxially grows silicon (Si) to form raised source and drain (S/D) features for an n-type device, and epitaxially grows silicon germanium (SiGe) to form raised S/D features for a p-type device.
Implementation Method 2
using techniques like cyclic deposition and etching to control growth orientation and doping
Data Source
AI summary
A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a substrate having first and second device regions. The first device region includes a first source/drain (S/D) region and the second device region includes a plurality of second S/D regions. The semiconductor device further includes a plurality of first recesses in the first S/D region and a plurality of second recesses, one in each of the second S/D regions. The semiconductor device further includes a first epitaxial feature having bottom portions and a top portion, wherein each of the bottom portions is in one of the first recesses and the top portion is over the first S/D region. The semiconductor device further includes a plurality of second epitaxial features each having a bottom portion in one of the second recesses. The second epitaxial features separate from each other.