Epitaxial Source/Drain Doping Profile for Multigate Gate Control
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Solution Overview
Problem
As multigate devices continue to scale, advanced techniques are needed to optimize multigate device reliability, as existing methods have not been entirely satisfactory in ensuring effective gate control and mitigating short-channel effects.
Innovation Solution
The implementation of epitaxial source/drain structures, which include semiconductor layers with specific dopant concentrations and geometries, to enhance the performance of multigate devices such as fin-like field-effect transistors (FETs) or gate-all-around (GAA) FETs, by replacing the traditional semiconductor substrate with a dielectric substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional semiconductor substrate is used, then device fabrication is straightforward, but gate control deteriorates and short-channel effects increase
Solution Approach 1:
The patent extracts the semiconductor substrate and replaces it with a dielectric substrate, removing the harmful interaction between the substrate and channel that causes short-channel effects. This extraction allows independent optimization of the channel region while maintaining gate control.
Solution Approach 2:
The patent employs composite material structures including epitaxial semiconductor layers grown on dielectric substrates, combined with selective doping regions and engineered interfaces. This composite approach enables simultaneous achievement of good gate control and reduced short-channel effects.
2Productivity
If device scaling continues, then transistor density increases, but device reliability deteriorates
Solution Approach 1:
The patent applies local quality by implementing selective doping regions with different dopant concentrations in different areas of the device. The epitaxial layers have tailored dopant profiles that locally optimize electrical characteristics while maintaining overall device scaling.
Solution Approach 2:
The patent changes material parameters by controlling dopant concentrations, epitaxial layer thicknesses, and composition gradients. These parameter changes enable device scaling while maintaining reliability through optimized electrical properties in scaled dimensions.
3Reliability
If epitaxial structures are implemented, then strain characteristics improve and sheet resistance decreases, but fabrication complexity increases
Solution Approach 1:
The patent performs preliminary action by forming the epitaxial semiconductor layers with predetermined dopant concentrations and compositions before subsequent processing steps. This preliminary structuring enables strain engineering and low sheet resistance to be built into the device architecture rather than added later.
Solution Approach 2:
The epitaxial growth process self-services by simultaneously achieving multiple objectives: forming the semiconductor layers, introducing dopants, creating strain fields, and defining device geometry. This self-service capability reduces the need for separate fabrication steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the reliability and performance of multigate devices by enhancing strain characteristics, reducing epi sheet resistance, and suppressing parasitic transistors, thereby maintaining effective gate control and mitigating short-channel effects.
Implementation Method 1
enhancing strain characteristics
Implementation Method 2
reducing epi sheet resistance
Data Source
AI summary
Epitaxial source/drain structures for enhancing performance of multigate devices, such as fin-like field-effect transistors (FETs) or gate-all-around (GAA) FETs, and methods of fabricating the epitaxial source/drain structures, are disclosed herein. An exemplary device includes a dielectric substrate. The device further includes a channel layer, a gate disposed over the channel layer, and an epitaxial source/drain structure disposed adjacent to the channel layer. The channel layer, the gate, and the epitaxial source/drain structure are disposed over the dielectric substrate. The epitaxial source/drain structure includes an inner portion having a first dopant concentration and an outer portion having a second dopant concentration that is less than the first dopant concentration. The inner portion physically contacts the dielectric substrate, and the outer portion is disposed between the inner portion and the channel layer. In some embodiments, the outer portion physically contacts the dielectric substrate.