Epitaxial Source Drain Structures for Gate Protection
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Solution Overview
Problem
Existing methods for scaling down semiconductor integrated circuits, such as MOSFETs, have not been entirely satisfactory in improving transistor performance due to limitations in source and drain feature configurations and materials, particularly in controlling short channel effects and carrier mobility.
Innovation Solution
A method for fabricating integrated circuit devices involves forming gate structures, lightly doped source and drain regions, and epitaxially growing semiconductor materials in recesses on both sides of the gate structures, with different materials used for n-channel and p-channel transistors to enhance carrier mobility and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then production efficiency is improved and costs are lowered, but short channel effects worsen and device performance deteriorates
Solution Approach 1:
The patent applies local quality by forming raised source and drain regions with different heights in different locations. Specifically, first raised source/drain regions are formed to a first height, then second raised source/drain regions are formed to a second height greater than the first height. This localized variation in geometry allows optimization of carrier mobility in critical regions while maintaining overall device scaling for high functional density.
Solution Approach 2:
The patent changes physical parameters by using different semiconductor materials with distinct properties. Epitaxial silicon is used for n-type raised source/drain regions while epitaxial silicon germanium is used for p-type raised source/drain regions. These material parameter changes enable enhanced carrier mobility and improved device performance despite continued geometry scaling.
2Length of moving object
If geometry size is decreased to increase functional density, then scaling benefits are achieved, but control over gate length and carrier mobility becomes more difficult
Solution Approach 1:
The patent applies preliminary action by forming mandrel structures and spacer structures before forming the final raised source/drain regions. The mandrels are formed first, then spacers are deposited around them, and finally the raised regions are epitaxially grown. This sequential preliminary structuring enables precise control of gate length and raised region dimensions even at scaled geometries.
Solution Approach 2:
The patent uses intermediary structures (mandrels and spacers) as mediators to achieve precise dimensional control. The mandrels serve as temporary intermediaries that define the initial geometry, and the spacers serve as intermediaries that transfer and refine the dimensional specifications to the final raised source/drain regions. This intermediary approach enables manufacturing precision during scaling.
3Ease of manufacture
If existing source and drain feature configurations are used, then manufacturing is simpler, but carrier mobility and device performance are not sufficiently enhanced
Solution Approach 1:
The patent applies local quality by implementing different material compositions and heights in different source/drain regions. First raised source/drain regions are formed with epitaxial silicon, then second raised source/drain regions are formed with epitaxial silicon germanium at a greater height. This localized differentiation enhances carrier mobility in specific regions while maintaining a manufacturing process that builds upon existing epitaxial growth techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves device performance by reducing short channel effects, increasing saturation current, and decreasing contact resistance, while providing better control over gate length and carrier mobility.
Implementation Method 1
epitaxially growing silicon germanium (SiGe) to form raised source and drain features
Data Source
AI summary
An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved protection for the bottom portion of the gate structure. In some embodiments, the method achieves improved protection for gate structure bottom by forming a recess on either side of the gate structure and placing spacers on the side walls of the gate structure, so that the spacers protect the portion of the gate structure below the gate dielectric layer.