Epitaxial Source Drain Growth for 3D ICs
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Solution Overview
Problem
Monolithic 3D IC fabrication faces challenges in forming source and drain semiconductor material with low resistivity at low temperatures, as high-temperature processing techniques used in conventional CMOS technology are not suitable for monolithic integration, potentially degrading existing device performance and dielectric materials.
Innovation Solution
The use of low-temperature (<450°C) epitaxial growth of in-situ doped source and drain material from a monocrystalline seeding surface, allowing for higher dopant concentration and reduced impurity introduction in the channel material, resulting in transistors with lower external resistance and improved channel mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature processing techniques are used to form source and drain semiconductor material with low resistivity, then the electrical resistance is reduced, but the performance of previously fabricated device levels is degraded
Solution Approach 1:
The patent changes the temperature parameter from conventional high-temperature processing (>800°C for epitaxial growth, >1000°C for ion implantation activation) to low-temperature processing (<450°C). This is achieved by using in-situ doped material deposition where dopants are incorporated during the deposition process itself, eliminating the need for subsequent high-temperature activation anneals. The low temperature prevents thermal degradation of previously fabricated device levels while still achieving low resistivity source and drain regions.
Solution Approach 2:
The patent replaces the conventional two-step process (material deposition followed by thermal activation) with a single-step in-situ doped deposition process. This substitution eliminates the mechanical/thermal activation step that causes damage to underlying devices, while achieving the same electrical activation of dopants through the deposition process itself.
2Reliability
If ion implantation followed by thermal activation is used to introduce dopants, then dopant activation is achieved, but high temperatures are required that are not suitable for monolithic 3D-IC integration
Solution Approach 1:
The patent replaces thermal activation with in-situ doped material deposition. Dopants are incorporated into the source and drain semiconductor material during the deposition process itself, achieving electrical activation without requiring subsequent high-temperature thermal processing. This eliminates the temperature conflict in monolithic 3D-IC integration while maintaining effective dopant activation.
Solution Approach 2:
The deposition process acts as an intermediary that simultaneously achieves both material formation and dopant activation in a single low-temperature step, replacing the need for separate high-temperature activation processing.
3Temperature
If in-situ doped material deposition is used, then low temperature processing is achieved, but dopant concentration and electrical activity may be insufficient
Solution Approach 1:
The patent optimizes deposition parameters including dopant concentration, deposition rate, and plasma power to achieve sufficient electrical activity at low temperatures. By carefully controlling these parameters, the in-situ doped deposition process achieves dopant activation levels comparable to or exceeding conventional high-temperature processes, while maintaining low processing temperatures suitable for monolithic 3D-IC integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of monolithic 3D ICs with finer source and drain pitches, higher channel mobility, and lower parasitic external resistance, while maintaining the performance and reliability of existing transistors, thus achieving denser and more efficient integrated circuit architectures.
Implementation Method 1
low-temperature (<450°C) epitaxial growth of in-situ doped source and drain material from a monocrystalline seeding surface
Data Source
AI summary
A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include monocrystalline source and drain material epitaxially grown from a monocrystalline channel material at a temperature low enough to avoid degradation of a lower level transistor structure and/or degradation of one or more low-k dielectric materials between the transistor levels. A highly conductive n-type silicon source and drain material may be selectively deposited at low temperatures with a high pressure CVD process. Multiple crystals of source drain material arranged in a vertically stacked multi-channel transistor structure may be contacted by a single contact metallization.