Epitaxial Source/Drain Junctions for Abrupt Profiles
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Solution Overview
Problem
Highly integrated semiconductor devices face challenges in forming source/drain regions with low electrical resistance and abrupt junction profiles due to limitations in ion implantation processes, which can lead to increased junction leakage current and difficulty in suppressing the short-channel effect.
Innovation Solution
The use of epitaxial layers with different germanium contents, formed in a semiconductor substrate, to create source/drain regions with improved electrical characteristics, where the first silicon germanium layer acts as a buffer and the second layer with higher germanium content fills the trenches, allowing for in-situ doping and heat treatment to form impurity regions without crystal defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ion implantation and high-temperature heat treatment are used to form source/drain regions, then impurity ions can be activated and diffused, but lateral diffusion lengths increase and crystal defects remain uncured
Solution Approach 1:
The patent changes the fundamental parameter of impurity introduction from ion implantation to in-situ doping during epitaxial growth. This allows impurity concentration and distribution to be controlled by growth conditions rather than high-temperature diffusion, achieving both activation and precise lateral profile control without the trade-off between diffusion and defect curing
Solution Approach 2:
The patent replaces the mechanical/physical process of ion implantation with a chemical epitaxial growth process. Impurities are incorporated during the epitaxial layer formation through in-situ doping, eliminating the need for subsequent high-temperature activation and diffusion steps that cause lateral spreading
2Length of stationary object
If sufficiently deep source/drain regions are formed using ion implantation and heat treatment, then channel length can be maintained, but abrupt junction profiles cannot be achieved
Solution Approach 1:
The patent performs preliminary doping during the epitaxial growth process itself, incorporating impurities into the lattice structure as the layer forms. This preliminary action achieves both deep source/drain regions and abrupt junction profiles simultaneously, eliminating the need for post-growth diffusion that would otherwise blur the junction boundaries
Solution Approach 2:
The patent changes the doping mechanism from thermal diffusion to in-situ incorporation during epitaxial growth. This allows precise control of impurity concentration and depth distribution, achieving abrupt junction profiles even at greater depths where traditional diffusion would cause significant lateral spreading
3Reliability
If shallow junction depths are used to suppress short-channel effect, then channel control is improved, but electrical resistance of source/drain regions increases
Solution Approach 1:
The patent applies local quality by creating highly doped regions precisely at the source/drain locations through in-situ doping during epitaxial growth. This localized high-concentration doping reduces electrical resistance in the source/drain regions while maintaining shallow overall junction depths to suppress short-channel effects
Solution Approach 2:
The patent uses composite epitaxial structures with different doping concentrations in different layers. The epitaxial layers contain high concentrations of dopants (e.g., phosphorus or boron) incorporated during growth, creating locally highly conductive regions that reduce resistance without increasing junction depth
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of semiconductor devices with reduced electrical resistance and improved junction leakage current characteristics, achieving shallow and abrupt junction profiles without high-temperature heat treatment, thus addressing the limitations of traditional ion implantation methods.
Implementation Method 1
forming epitaxial layers in the active trenches, respectively. The respective epitaxial layers may be formed by sequentially stacking first and second layers, the first and second layers may be formed of a semiconductor layer having a lattice constant greater than the semiconductor substrate
Implementation Method 2
after implanting impurity ions into the semiconductor substrate, the source/drain regions may be formed by activating and diffusing the impurity ions at a high temperature of about 800° C. or more
Data Source
AI summary
Provided are methods of fabricating a semiconductor device including a metal oxide semiconductor (MOS) transistor. The methods include forming a gate pattern on a semiconductor substrate. The semiconductor substrate is etched using the gate pattern as an etching mask to form a pair of active trenches spaced apart from each other in the semiconductor substrate. Epitaxial layers are formed in the active trenches, respectively. The respective epitaxial layers are formed by sequentially stacking first and second layers. The first and second layers are formed of a semiconductor layer having a lattice constant greater than the semiconductor substrate, and a composition ratio of the second layer is different from that of the first layer. Semiconductor devices having the first and second layers are also provided.