Match-Stick Epitaxial Source/Drain Structures for Sub-10 nm Fin Scaling
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Solution Overview
Problem
The scaling of features in integrated circuits to smaller sizes, particularly below the 10 nanometer node, is hindered by variability in conventional fabrication processes, necessitating the introduction of new methodologies or technologies to optimize performance and density.
Innovation Solution
The implementation of advanced fabrication techniques such as pitch quartering and merged fin pitch quartering approaches for semiconductor fin formation, combined with the use of epitaxial source or drain structures and multi-layer trench isolation structures, to enhance integration density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used, then manufacturing simplicity is maintained, but manufacturing precision deteriorates at 10 nanometer node and smaller
Solution Approach 1:
The patent applies pitch quartering by dividing the fin formation process into multiple patterning stages. First mandrels are formed, then spacers are deposited and patterned, followed by additional spacer formation to achieve quarter-pitch features. This segmentation enables manufacturing precision at 10nm node by breaking down the complex patterning into manageable steps, each with controlled precision requirements.
Solution Approach 2:
The patent uses preliminary actions by forming sacrificial mandrels and spacers before final fin patterning. The mandrels are formed first, then spacers are deposited conformally on mandrel sidewalls. These preliminary structures serve as templates that guide subsequent etching steps, ensuring precise fin placement and dimensions are achieved before the actual fin formation occurs.
2Productivity
If feature size is scaled down to increase density, then productivity is improved, but manufacturing precision deteriorates due to process variability
Solution Approach 1:
The patent employs self-aligned spacer formation where spacers are deposited conformally on mandrel sidewalls and then etched back. The mandrels themselves serve as the alignment reference for spacer placement, eliminating the need for separate lithography alignment steps. This self-service approach maintains manufacturing precision while enabling pitch quartering to quadruple integration density, as each spacer automatically aligns to its mandrel without additional overlay variability.
3Manufacturing precision
If new fabrication methodologies are introduced to improve precision, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple functions into the spacer structures. The same spacers that define fin pitch also serve as etch masks for fin formation and as alignment references for subsequent gate patterning. By combining patterning, masking, and alignment functions into single spacer structures, the patent reduces the number of separate process steps needed, thereby managing device complexity while achieving high manufacturing precision through pitch quartering.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These techniques enable the fabrication of integrated circuit structures with improved density and performance, overcoming the limitations of conventional processes and enabling further scaling to smaller technology nodes.
Implementation Method 1
epitaxial source or drain structures for advanced integrated circuit structure fabrication
Data Source
AI summary
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. A gate electrode is over the upper fin portion of the fin, the gate electrode having a first side opposite a second side. A first epitaxial source or drain structure is embedded in the fin at the first side of the gate electrode. A second epitaxial source or drain structure is embedded in the fin at the second side of the gate electrode, the first and second epitaxial source or drain structures comprising silicon and germanium and having a match-stick profile.