Epitaxial Source-Drain Stressing in Dummy Gate MOSFETs

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Solution Overview

Problem

The challenge in semiconductor manufacturing is to prevent crystal defects caused by high concentrations of atoms with different lattice constants in mixed crystal layers while effectively applying stress to channel regions for enhanced carrier mobility, which existing methods fail to achieve due to counteraction from dummy gate electrodes suppressing the stress applied by these layers.

Innovation Solution

A method involving the formation of a dummy gate electrode, recess etching, and epitaxial growth of mixed crystal layers on silicon substrates, followed by removal of the dummy gate to allow effective stress application to the channel region through the gate insulating film, thereby preventing crystal defects and enhancing carrier mobility.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If mixed crystal layers are formed to apply stress to channel regions, then carrier mobility is enhanced, but crystal defects occur due to high concentrations of atoms with different lattice constants

Engineering Contradiction:
Improvecarrier mobilityVSAvoidcrystal defect prevention
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent applies different Ge concentrations to different regions: the mixed crystal layers adjacent to the channel have lower Ge concentration (5-20 at%) to prevent crystal defects, while regions farther from the channel have higher Ge concentration for effective stress application. This local quality differentiation resolves the contradiction between stress effectiveness and crystal quality.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the Ge concentration parameter spatially across the mixed crystal layer structure. By controlling the Ge concentration to be 5-20 at% in regions adjacent to the channel and higher in other regions, the patent optimizes both stress application and crystal quality, preventing the harmful effects of high Ge concentration near the channel while maintaining stress benefits.

Inventive Principle:
Principle #35Parameter changes

2Ease of manufacture

If dummy gate electrodes are used during manufacturing, then process control is improved, but stress application to channel regions is suppressed due to counteraction from the dummy gate

Engineering Contradiction:
Improveprocess controlVSAvoidstress application to channel
Core Design Contradiction:
Ease of manufactureVSStress or pressure

Solution Approach 1:

The patent performs preliminary stress application through mixed crystal layers formed before the final gate electrode. The stress is applied during the epitaxial growth stage, and the dummy gate is subsequently removed. This preliminary action allows stress to be established before the dummy gate can potentially counteract it, resolving the contradiction between using dummy gates for process control and maintaining effective stress application.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Instead of applying stress after gate formation (where dummy gates would counteract), the patent inverts the sequence by applying stress through mixed crystal layers first, then removing the dummy gate. This inversion ensures stress is applied when the dummy gate is still present but will be removed before final device operation, eliminating the counteraction problem while maintaining process control benefits.

Inventive Principle:
Principle #13The other way round (Inversion)

3Stress or pressure

If high Ge concentration is used in mixed crystal layers, then stress application is enhanced, but crystal defects increase due to lattice constant mismatch

Engineering Contradiction:
Improvestress magnitudeVSAvoidcrystal quality
Core Design Contradiction:
Stress or pressureVSManufacturing precision

Solution Approach 1:

The patent applies local quality by differentiating Ge concentration based on position: 5-20 at% Ge in regions adjacent to the channel where crystal quality is critical, and higher Ge concentration in regions farther from the channel where stress application is prioritized. This spatial differentiation resolves the contradiction between stress magnitude and crystal quality.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the Ge concentration parameter across different spatial regions of the mixed crystal layers. By controlling Ge concentration to be 5-20 at% near the channel and higher in other regions, the patent achieves both adequate stress application and high crystal quality, preventing the defects that would result from uniformly high Ge concentration.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively strains the channel region, increasing carrier mobility and preventing crystal defects, leading to improved transistor characteristics such as on/off ratios and reduced parasitic capacitance.

Implementation Method 1

a mixed crystal layer that is composed of silicon and an atom having a lattice constant different from that of silicon is epitaxially grown on the surface of the recess region

Methodology Applied
Scientific EffectStress:

Implementation Method 2

a mixed crystal layer that is composed of silicon and an atom having a lattice constant different from that of silicon is epitaxially grown on the surface of the recess region

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS20240204102A1Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process
Publication Date: 2024.06.20 SONY GROUP CORP
  • US20240204102A1 patent drawing
  • US20240204102A1 patent drawing
  • US20240204102A1 patent drawing

AI summary

A semiconductor device in which sufficient stress can be applied to a channel region due to lattice constant differences.