Epitaxial Source-Drain Formation for Vertical Transistor Fin Stability
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Solution Overview
Problem
VTFET devices face challenges in forming reliable and consistent source-drain regions due to time-consuming and unreliable dopant ion diffusion, leading to higher on-resistance and reliability issues, especially with fin dimensions in the range of 5-10 nanometers where selective etching can result in unstable or collapsing fins.
Innovation Solution
A method involving the formation of multi-layer fin mandrels, selective etching to create space for epitaxial growth of doped source-drain regions beneath the fins, using a stack of semiconductor layers including SiGe, undoped crystalline Si, and protective layers to support the fins during etching, and epitaxial growth of doped source-drain regions with angled surfaces for stable fin formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If dopant ion diffusion is used to form source-drain regions, then the process is simpler, but the method is time-consuming and unreliable leading to higher on-resistance
Solution Approach 1:
The patent changes the fundamental parameter of source-drain region formation from dopant ion diffusion to epitaxial growth. This parameter change enables direct formation of doped semiconductor regions with controlled doping concentrations during the growth process, eliminating the time-consuming and unreliable diffusion process while achieving lower on-resistance and higher device reliability
Solution Approach 2:
The patent replaces the thermal diffusion process with an epitaxial growth process. Instead of relying on thermal diffusion of dopant ions through existing crystal structures, the method uses epitaxial growth to directly form doped semiconductor regions, substituting a more precise and controllable growth mechanism for the less reliable diffusion process
2Manufacturing precision
If selective etching is used to create source-drain regions, then the method provides geometric control, but the fins become unstable or collapsing at 5-10 nanometer dimensions
Solution Approach 1:
The patent applies preliminary action by forming sacrificial mandrels and protective layers before the epitaxial growth process. These structures are prepared in advance to guide and support the subsequent epitaxial growth of source-drain regions, ensuring both geometric precision and structural stability during the formation process
Solution Approach 2:
The patent introduces sacrificial mandrels and protective layers as intermediary structures. These intermediaries facilitate the precise formation of source-drain regions by providing templates and support during epitaxial growth, then are selectively removed to reveal the final structure, maintaining both geometric control and fin stability
3Reliability
If epitaxial growth is used to form source-drain regions, then device reliability improves, but the process complexity increases with multi-layer stacks
Solution Approach 1:
The patent segments the fabrication process into distinct stages: forming sacrificial mandrels, depositing protective layers, performing selective etching, and conducting epitaxial growth. This segmentation allows each step to be optimized independently, managing overall process complexity while achieving reliable source-drain region formation through controlled epitaxial growth
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of stable and reliable epitaxially grown source-drain regions beneath the fins, reducing on-resistance and improving device reliability by providing a consistent and efficient method for creating VTFET fin transistors with enhanced performance.
Implementation Method 1
selectively etching the sacrificial epitaxial layer beneath the fin mandrels
Implementation Method 2
epitaxial growth of doped source-drain regions beneath the fins
Data Source
AI summary
A method of forming a semiconductor device includes forming a sacrificial epitaxial layer upon a substrate, forming a stack of semiconductor material layers upon the sacrificial epitaxial layer, forming fin mandrels for vertical transistors, selectively etching the sacrificial epitaxial layer beneath the fin mandrels, forming source-drain regions beneath the fin mandrels, selectively removing portions of the fin mandrels creating the fins, and forming source-drain contacts electrically connected to the source-drain regions.