Epitaxial Source/Drain Interface for Lower-Resistance Backside Vias
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Solution Overview
Problem
As integrated circuits scale down, power rails experience increased voltage drop and power consumption due to limited contact area between source/drain features and backside power rails, necessitating improved power rail structures for reduced resistance and enhanced performance.
Innovation Solution
The implementation of backside power rails with enlarged source/drain features interfacing via additional lateral etching to break through dielectric layers, increasing the contact area with backside vias, and using epitaxial growth to enhance the interface, thereby reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional stacked-up power rail structure is used, then device integration is maintained, but voltage drop and power consumption increase due to limited contact area
Solution Approach 1:
The patent transitions from a conventional planar contact interface to a three-dimensional enlarged lower section of the source/drain feature that extends downward to interface with the backside via. This vertical dimensionality change increases the contact area between the source/drain feature and the backside power rail, thereby reducing contact resistance and power consumption without increasing the planar footprint.
Solution Approach 2:
The enlarged lower section of the source/drain feature is nested within the substrate thickness, extending downward to contact the backside via. This nesting approach allows the contact interface to be formed within the existing substrate volume, increasing contact area without requiring additional lateral space that would increase device footprint.
2Loss of energy
If contact area is increased to reduce resistance, then power consumption decreases, but device footprint and complexity increase
Solution Approach 1:
The patent resolves the complexity issue by extending the source/drain feature in the vertical dimension rather than laterally. The enlarged lower section forms a downward-protruding structure that increases contact area with the backside via while maintaining a compact planar footprint, thus avoiding increased device complexity.
Solution Approach 2:
The source/drain feature exhibits local quality variation with an enlarged lower section specifically at the contact region with the backside via, while the upper portion maintains its conventional dimensions. This localized enlargement concentrates the resistance-reduction benefit at the critical contact interface without unnecessarily increasing the overall device structure.
3Area of stationary object
If lateral etching is performed to enlarge source/drain feature, then contact area with backside via increases, but manufacturing process complexity increases
Solution Approach 1:
The patent applies preliminary patterning and etching steps that define the enlarged lower section geometry before subsequent epitaxial growth. By pre-forming the lateral extensions of the source/drain feature, the subsequent epitaxial growth naturally follows this predetermined geometry, simplifying the overall manufacturing process compared to attempting to form complex 3D structures in a single step.
Solution Approach 2:
The epitaxial growth process self-aligns to the pre-formed lateral extensions of the source/drain feature, automatically conforming to the desired enlarged lower section geometry. This self-service approach allows the material growth process to naturally create the complex 3D structure without requiring additional complex patterning or etching steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power rail resistance and enhances device integration by increasing the number of metal tracks and gate density, leading to improved performance and reduced power consumption.
Implementation Method 1
growing an epitaxial source/drain feature in the source/drain trench
Data Source
AI summary
A semiconductor structure includes an isolation structure; first and second source/drain (S/D) features over the isolation structure, defining a first direction from the first S/D feature to the second S/D feature from a top view; one or more channel layers connecting the first and the second S/D features; a gate structure between the first and the second S/D features and engaging each of the one or more channel layers; and a via structure under the first S/D feature and electrically connecting to the first S/D feature. In a cross-sectional view perpendicular to the first direction, the via structure has a profile that widens and then narrows along a bottom-up direction.