Epitaxial Straining Materials for Semiconductor Device Performance
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Solution Overview
Problem
Current methods for creating tensile and compressive strains in semiconductor devices require additional materials and complex processing, resulting in higher costs and limited strain levels, which are not optimally effective for maximizing the performance of both n-type (NFETs) and p-type (PFETs) devices within integrated circuits.
Innovation Solution
The method involves epitaxially growing straining materials like SiGe or Si:C directly on a polysilicon layer of a gate stack structure, applying physical biaxial strain through lattice constant mismatch, thereby enhancing device performance by providing tailored tensile or compressive strains for NFETs and PFETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If liners on gate sidewalls are used to selectively induce strain, then tensile strain is applied to NFET and compressive strain to PFET, but additional materials and complex processing are required resulting in higher cost
Solution Approach 1:
The patent extracts the straining function from the gate sidewall liners and transfers it directly to the channel region by epitaxially growing strained semiconductor material (e.g., SiGe for PFET, Si:C for NFET) directly on the channel. This eliminates the need for liner materials and their associated deposition and removal processes, reducing manufacturing complexity while maintaining the strain-induced performance enhancement.
Solution Approach 2:
The epitaxial growth process serves multiple functions simultaneously: it forms the channel structure, introduces the desired strain through lattice mismatch, and defines the device geometry. This multi-functional approach replaces the separate liner-based strain induction method, reducing the number of process steps and materials required.
2Reliability
If liners on gate sidewalls are used to induce strain, then strain is applied closer to the device, but the level of strain is typically moderate (on the order of 100s of MPa)
Solution Approach 1:
The patent changes the material composition parameter of the channel itself by epitaxially growing strained semiconductor material with controlled composition (e.g., varying Ge content in SiGe or C content in Si:C). This allows direct control of the strain magnitude through composition adjustment, enabling higher strain levels (exceeding 100s of MPa) compared to liner-based methods, while the strain is applied directly where needed in the channel region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases electron mobility and device performance by applying targeted strains, improving the characteristics of both NFETs and PFETs without the need for additional materials or complex processing, thereby reducing costs and enhancing strain levels.
Implementation Method 1
applying physical biaxial strain through lattice constant mismatch
Implementation Method 2
epitaxially growing straining materials like SiGe or Si:C directly on a polysilicon layer of a gate stack structure
Data Source
AI summary
Semiconductor devices are provided which have a tensile and/or compressive strain applied thereto and methods of manufacturing. The structure includes a gate stack comprising an oxide layer, a polysilicon layer and sidewalls with adjacent spacers. The structure further includes an epitaxially grown straining material directly on the polysilicon layer and between portions of the sidewalls. The epitaxially grown straining material, in a relaxed state, strains the polysilicon layer.