Epitaxial Super Junction Semiconductor Wafer Processing
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Solution Overview
Problem
Conventional methods for processing semiconductor wafers with high breakdown voltage and low on-resistance require numerous processing steps and result in non-uniform depletion layers due to undulate pn junction surfaces, making it difficult to achieve precise uniformity in impurity profiles and arrangement of super junction structures.
Innovation Solution
A method involving the sequential growth and etching of epitaxial semiconductor layers to form pillar-like structures with controlled thickness and dopant concentrations, allowing for uniform impurity profiles and vertical pn junctions, reducing the number of processing steps and improving structural uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple epitaxial layers are stacked and ion implantation/diffusion steps are repeated to form super junction structure, then high breakdown voltage and low on-resistance are achieved, but the number of processing steps becomes extremely large
Solution Approach 1:
The patent divides the formation of super junction structure into separate stages: first forming trenches in the first conductivity type layer, then filling with second conductivity type material, and finally forming additional trenches and filling with first conductivity type material. This segmentation allows the complex multi-layer structure to be built systematically with controlled processing steps rather than requiring repeated implantation cycles.
Solution Approach 2:
The patent transitions from vertical stacking of multiple epitaxial layers (thickness direction) to lateral formation of alternating conductivity type regions through trench etching and filling. By etching trenches through the layer and filling horizontally, the super junction structure is formed in the planar dimension rather than requiring multiple vertical deposition cycles, significantly reducing process complexity.
2Reliability
If pillar-like semiconductor regions with multiple impurity diffusion regions are formed, then super junction structure is achieved, but the side surfaces have undulate form causing non-uniform depletion layer spread
Solution Approach 1:
The patent performs preliminary trench etching to define precise vertical boundaries before filling with oppositely doped material. By pre-establishing the trench geometry with vertical sidewalls through controlled etching, the subsequent filling process automatically produces regions with uniform width and vertical interfaces, ensuring uniform depletion layer spread without requiring post-formation correction of undulate surfaces.
3Reliability
If oblique ion implantation is used to form pillar-like semiconductor regions, then super junction structure is achieved, but large trench width is required making it difficult to arrange multiple structures
Solution Approach 1:
Instead of forming wide trenches and using oblique implantation angles to create narrow pillars, the patent inverts the approach by etching narrow vertical trenches first, then filling them completely with oppositely doped material. This inversion allows precise control of the final pillar width through the trench definition step, enabling high-density arrangement of multiple super junction structures on the wafer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of semiconductor wafers with uniformly spread depletion layers and reduced resistance, achieving high breakdown voltage and low on-resistance while simplifying the processing steps and ensuring precise control over layer thickness and dopant distribution.
Implementation Method 1
growing a first epitaxial semiconductor layer of the first general conductivity type from the semiconductor wafer
Implementation Method 2
etching the first epitaxial semiconductor layer to form a plurality of trenches
Implementation Method 3
ions of a p type impurity are implanted into the openings to form p type semiconductor regions
Implementation Method 4
the ions of the p type impurity are diffused; thereby a wafer with a super junction structure
Data Source
AI summary
Formation and etching of an n type epitaxial layer and formation and etching of a p type epitaxial layer are alternately performed on the semiconductor substrate for at least three times to form all semiconductor layers, of the epitaxial layers. Thereby, impurity concentration profiles of the semiconductor layers can be uniform, and pn junctions can be formed vertically to a wafer surface. Furthermore, the semiconductor layers can each be formed with a narrow width, so that impurity concentrations thereof are increased. With this configuration, high breakdown voltage and low resistance can be achieved.