Epitaxial Support Pillars for Stable 3D Memory Access Tiers
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Solution Overview
Problem
In the fabrication of vertical three-dimensional (3D) memory devices, the shrinking design rules lead to limited semiconductor space, increasing the risk of deformation and breakage of silicon platforms during processing, particularly due to cantilevered structures that lack sufficient support.
Innovation Solution
The formation of support pillars using multiple, alternating layers of silicon germanium (SiGe) and silicon (Si) materials, deposited in third vertical openings, provides structural support to silicon platforms, mitigating deformation and breakage by acting as a secondary support mechanism during subsequent fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If design rules are shrunk to increase memory density, then productivity is improved, but the structural stability of access devices deteriorates leading to deformation and breakage
Solution Approach 1:
The patent divides the support structure into multiple discrete support pillars distributed throughout the silicon platform. Each pillar is a separate structural element that collectively provides comprehensive support, preventing deformation and breakage while allowing continued scaling of design rules for increased memory density.
Solution Approach 2:
The support pillars act as intermediary structural elements between the silicon substrate and the overhanging silicon platforms. These pillars mediate the mechanical stress and provide necessary support, enabling the fabrication of high-density memory structures without compromising the structural integrity of access devices.
2Area of stationary object
If larger silicon platforms are formed for memory cells, then the area available for memory fabrication is improved, but the platforms become cantilevered and prone to deformation or breakage
Solution Approach 1:
The support structure is segmented into multiple discrete pillars rather than a continuous support structure. This segmentation allows large silicon platforms to be supported at multiple distributed points, maintaining platform area for memory fabrication while preventing cantilevered deformation through comprehensive structural support.
Solution Approach 2:
The patent introduces vertical support elements (pillars extending in the vertical dimension) to support the horizontal silicon platforms. This dimensional approach allows large platforms to maintain their area while gaining vertical support structure that prevents deformation and breakage of cantilevered regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively prevents deformation and breakage of silicon platforms, ensuring reliable and stable fabrication of vertical 3D memory devices by providing additional structural support and maintaining the integrity of the silicon platforms throughout the processing stages.
Implementation Method 1
multiple alternating layers of silicon germanium (SiGe) and single crystalline silicon (Si) are epitaxially grown in repeating iterations to form a vertical stack
Data Source
AI summary
Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes formed in tiers. And, more particularly, to multiple, alternating silicon germanium (SiGe) and single crystalline silicon (Si) in different thicknesses to form tiers in which to form the horizontal access devices in vertical three-dimensional (3D) memory. The horizontally oriented access devices can have a first source/drain regions and a second source drain regions separated by single crystalline silicon (Si) channel regions. The single crystalline silicon (Si) channel regions can include a dielectric material to provide support structure to the single crystalline channel regions when forming the horizontal access devices in vertical three-dimensional (3D) memory. Horizontally oriented access lines can connect to gate structures opposing the channel regions. Vertical digit lines coupled to the first source/drain regions.