Epitaxial Growth Tile Orientation for Uniformity
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Solution Overview
Problem
Semiconductor fabrication processes face challenges in achieving uniformity due to varying pattern densities, particularly in epitaxial growth and chemical mechanical planarization (CMP) techniques, where existing methods fail to adequately compensate for differences in pattern densities between active and inactive regions.
Innovation Solution
A tiling strategy is developed where the same data set is used to derive mask sets for both polysilicon deposition and epitaxial growth, allowing the reuse of tiles to optimize epitaxial growth independently of trench CMP needs, thereby decoupling the requirements of both processes and ensuring better uniformity and growth characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the same tile pattern is reused for both trench CMP and epitaxial growth, then process simplicity is maintained, but suboptimal results are produced for epitaxial growth compensation
Solution Approach 1:
The invention divides the tile management system into separate segments: a first set of tiles generated from a first data set for trench CMP, and a second set of tiles generated from a second data set for epitaxial growth. This segmentation allows independent optimization of each tile set for its specific process without increasing overall system complexity.
Solution Approach 2:
The invention maintains a universal data set structure that can serve multiple purposes. The same overall data set framework is used to generate both trench CMP mask sets and epitaxial growth mask sets, allowing a single data management system to support multiple tile generation purposes with process-specific optimizations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for improved process uniformity and tailored growth rates by orienting epitaxial tiles to favor desired growth rates and facets, effectively compensating for global and local pattern density effects, and optimizing both polysilicon deposition and epitaxial growth without reconfiguring the trench CMP mask.
Implementation Method 1
when epitaxial growth processes are used to form silicon germanium alloy films on CMOS substrates
Implementation Method 2
the rate and uniformity of chemical mechanical planarization (CMP) techniques employed in conjunction with shallow trench isolation (STI) processes
Data Source
AI summary
A method for making a semiconductor device is provided which comprises (a) creating a data set (301) which defines a set of tiles for a polysilicon deposition process; (b) deriving a polysilicon deposition mask set (311) from the data set, wherein the polysilicon deposition mask set includes a plurality of polysilicon tiles (303); (c) deriving an epitaxial growth mask set (321) from the data set, wherein the epitaxial growth mask set includes a plurality of epitaxial tiles (305); and (d) using the polysilicon deposition mask set and the epitaxial growth mask set to make a semiconductor device (331); wherein the epitaxial growth mask set is derived from the data set by using at least a portion of the tile pattern defined in the data set for at least a portion of the tile pattern defined in the epitaxial deposition mask set.