Epitaxial Transistor Structure with Diffusion Barrier for Leakage Control

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Solution Overview

Problem

As integrated circuit devices are scaled down, there is a tradeoff between performance (speed) and leakage (power usage) due to heavier well doping, which increases charge carrier scattering and leads to higher leakage rates, while heavier source/drain doping causes short channel effects.

Innovation Solution

The formation of high-quality crystalline channel regions in epitaxially grown semiconductor layers above deep n-wells and p-wells, with an additional epitaxially grown diffusion barrier layer to inhibit dopant diffusion, and epitaxially grown source/drain regions with a low thermal budget to maintain high purity and allow heavy doping of wells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If heavier well doping is used to reduce body resistance, then body resistance decreases, but charge carrier scattering increases leading to higher leakage rates

Engineering Contradiction:
Improvebody resistanceVSAvoidleakage rate
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

An undoped semiconductor layer is introduced as an intermediary between the heavily doped well and the channel region. This intermediate layer acts as a diffusion barrier that prevents dopant migration from the well into the channel, thereby maintaining low body resistance through heavy well doping while preventing charge carrier scattering and leakage in the channel region.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The semiconductor structure is segmented into distinct regions: a heavily doped well region, an undoped intermediate layer, and a pure channel region. This segmentation allows each region to be optimized independently - the well for low resistance and the channel for low leakage - without compromising the other.

Inventive Principle:
Principle #1Segmentation

2Reliability

If heavier source/drain doping is used to reduce source/drain resistance, then source/drain resistance decreases, but junction depth increases leading to short channel effects

Engineering Contradiction:
Improvesource/drain resistanceVSAvoidshort channel effects
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The undoped semiconductor layer serves as an intermediary that blocks dopant diffusion from the source/drain regions into the channel. This allows heavy source/drain doping to achieve low resistance while the undoped layer prevents the dopants from migrating deep into the channel, thereby avoiding short channel effects.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If device size is reduced to improve integration density, then productivity increases, but control over doping diffusion becomes more difficult leading to higher leakage

Engineering Contradiction:
Improveintegration densityVSAvoidleakage rate
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The undoped semiconductor layer provides a reliable diffusion barrier that is effective even in scaled-down devices. This intermediary layer ensures precise control over doping profiles in miniaturized transistors, preventing leakage despite the reduced device dimensions and tighter integration density.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables high-performance transistors with reduced leakage rates and short channel effects, achieving high purity in channel regions while allowing heavy doping of wells, thus optimizing performance and power usage.

Implementation Method 1

an additional layer of epitaxially grown semiconductor formed above the wells and below the channel regions. The additional layer acts as a diffusion barrier layer

Methodology Applied
Scientific EffectDiffusion barrier: Diffusion Barrier

Implementation Method 2

High quality crystalline channel regions for the transistors are formed in a layer of epitaxially grown semiconductor

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS10103064B2Transistor structure including epitaxial channel layers and raised source/drain regions
Publication Date: 2018.10.16 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10103064B2 patent drawing
  • US10103064B2 patent drawing
  • US10103064B2 patent drawing

AI summary

The present disclosure provides an integrated circuit device including n-channel and p-channel MOSFETs. The MOSFETs include epitaxial grown raised source/drain regions and epitaxial grown channel regions. An epitaxially grown diffusion barrier layer separates the epitaxial grown channel regions from underlying deep n-wells and p-wells. The epitaxial source/drain regions allow for a low thermal budget that in combination with the diffusion barrier layer allows the deep n-wells and p-wells to be heavily doped while preserving high purity in the channel layers.