Epitaxial Vertical Selector for Resistive Memory Density
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Solution Overview
Problem
Current non-volatile memory technologies, such as MRAM, face challenges in achieving high memory density and efficient current conduction due to limitations in the spacing and conductivity between memory cells, particularly when using two-terminal resistive switching memory elements.
Innovation Solution
The integration of an epitaxially grown semiconductor column with a gate dielectric and conductive gate line, along with a bottom electrode, forms an efficient vertical transistor structure that reduces spacing and enhances conductivity, allowing for increased memory density and improved current conduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional two-terminal resistive switching memory elements are used, then the memory structure is simple, but the spacing between memory cells is large and conductivity is poor
Solution Approach 1:
The patent transitions from planar memory cell layout to a vertical three-dimensional structure by growing semiconductor columns perpendicular to the substrate. This dimensional change allows memory cells to be stacked vertically, dramatically reducing the lateral spacing between cells while maintaining electrical performance and simplifying the overall structure through vertical integration of the selector, memory element, and electrode components.
2Quantity of substance
If larger semiconductor selector diameters are used, then current conduction is improved, but memory density decreases
Solution Approach 1:
The patent employs epitaxial growth to create highly doped semiconductor columns with controlled diameter and optimized electrical properties. By changing the doping parameters and growth conditions, the semiconductor material achieves high conductivity in a minimal volume, allowing small-diameter columns to carry sufficient current while maximizing memory cell density in the array.
3Manufacturing precision
If precise alignment is required for manufacturing, then electrical connection accuracy is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent implements self-aligned manufacturing processes where the semiconductor column growth is automatically positioned over the memory element footprint, and the bottom electrode is subsequently formed to contact the column. This self-alignment mechanism eliminates the need for complex photolithographic alignment steps between layers, significantly reducing manufacturing precision requirements and simplifying the fabrication process while ensuring accurate electrical connections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly increases memory density and conductivity, enabling the use of smaller semiconductor selector diameters and facilitating the switching of two-terminal resistive switching memory elements with reduced manufacturing complexity and alignment requirements.
Implementation Method 1
an epitaxial semiconductor column... electrically connecting the memory element with the gate line
Implementation Method 2
gate dielectric separates the epitaxial semiconductor column from the electrically conductive gate line
Data Source
AI summary
A magnetic memory array having an epitaxially grown vertical semiconductor selector connected with a two terminal resistive switching memory element via a bottom electrode such as TaN. An electrically conductive contact such as tungsten (W) or TaN can be included between the vertical semiconductor channel and the TaN bottom electrode. The electrically conductive contact and the TaN bottom electrode can both be formed by a damascene process wherein an opening is formed in an oxide layer and a metal is deposited into the opening. A chemical mechanical polishing process can then be performed to remove portions of the metal that extend out of the opening in the oxide layer over the oxide surface.