Single Crystalline Epitaxial Structure Void Prevention
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Solution Overview
Problem
Conventional methods for forming single crystalline silicon structures in semiconductor devices often result in voids due to incomplete epitaxial growth, which reduces the reliability of vertically stacked semiconductor devices.
Innovation Solution
The solution involves forming a first epitaxial layer pattern with flat side surfaces in contact holes and a second epitaxial layer pattern that fills a trench extending over the first epitaxial layer pattern, ensuring complete coverage and preventing voids by maintaining a misalignment margin between 5 nm to 30 nm, thereby facilitating vertical growth and reducing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If selective epitaxial growth is performed to form a single crystalline silicon layer on the semiconductor substrate, then a single crystalline structure is formed for vertical stacking, but voids are generated in the lower region due to source gas not being provided to the region under the contact region
Solution Approach 1:
The patent introduces a planarization layer to fill the void space created by the contact hole geometry, transforming a three-dimensional growth problem into a two-dimensional planar surface problem. This allows subsequent epitaxial layers to grow uniformly without encountering the void region, ensuring complete coverage and eliminating reliability issues associated with void formation.
Solution Approach 2:
The patent performs planarization before the final epitaxial growth step by forming a planarization layer that fills the contact hole voids. This preliminary action prepares a flat, void-free surface that enables complete and uniform epitaxial growth in subsequent processing steps, preventing the source gas distribution problem from occurring during critical layer formation.
2Productivity
If the line width or interval of patterns is narrowed to increase integration degree, then device integration is improved, but electrical resistance of patterns is greatly increased
Solution Approach 1:
The patent transitions from two-dimensional planar device architecture to three-dimensional vertically stacked architecture. By stacking multiple semiconductor unit elements vertically, the integration degree increases without further narrowing the lateral dimensions of individual patterns, thereby maintaining acceptable electrical resistance while achieving higher integration.
Solution Approach 2:
The patent divides the semiconductor device into multiple vertically stacked unit elements, each functioning as a separate active region. This segmentation allows the device to achieve higher integration through vertical stacking rather than lateral compression, preserving the electrical characteristics of each segment while increasing overall device capacity.
3Ease of manufacture
If conventional epitaxial growth method is used to form single crystalline silicon structure, then manufacturing process is simplified, but voids are generated reducing device reliability
Solution Approach 1:
The patent introduces a planarization step before the critical epitaxial growth phase. This preliminary action of forming a planarization layer eliminates the void formation problem by providing a flat, void-free surface for subsequent epitaxial growth, ensuring device reliability while maintaining process simplicity through the addition of only one preparatory step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the integration density and reliability of semiconductor devices by preventing voids and improving electrical characteristics through precise alignment and growth control.
Implementation Method 1
a selective epitaxial growth (SEG) process for forming a single crystalline silicon layer on the semiconductor substrate as a seed
Data Source
AI summary
A single crystalline structure includes a first insulation interlayer pattern, a first epitaxial layer pattern, a second insulation interlayer pattern, and a second epitaxial layer pattern. The first insulation interlayer pattern includes a contact hole that exposes a single crystalline seed. The first epitaxial layer pattern fills up the contact hole. The second insulation interlayer pattern is formed on the first insulation interlayer pattern and the first epitaxial layer pattern. The second insulation interlayer pattern has a trench that partially exposes the first epitaxial layer pattern and has an end disposed over an upper surface of the first epitaxial layer pattern. The second epitaxial layer pattern fills up the trench. Thus, voids are not generated in the second epitaxial layer pattern and a semiconductor device having the single crystalline structure exhibits improved reliability.