Epitaxial Wafer Thermal Buffer Ring for Stress-Free Coating

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Solution Overview

Problem

Existing semiconductor wafer epitaxial coating processes face issues with stress-induced dislocations and slips, undesired crystal defects, autodoping, backside halo, and nanotopography effects, particularly at high pretreatment and deposition temperatures, which are not effectively addressed by previous solutions.

Innovation Solution

A ring acting as a thermal buffer is positioned between the semiconductor wafer and a porous susceptor with a gas-permeable structure, preventing direct contact and allowing gas diffusion to remove dopants and native oxide products, while maintaining thermal equilibration to reduce stress and defects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If a porous susceptor is used to remove dopants and oxide products, then autodoping and halo effects are reduced, but stress-induced dislocations and slips occur due to direct thermal contact

Engineering Contradiction:
Improveautodoping and halo effectsVSAvoidstress-induced dislocations and slips
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

A ring structure is introduced as an intermediary element between the porous susceptor and the semiconductor wafer. This ring acts as a thermal buffer that mediates the thermal interaction, allowing the porous susceptor to maintain its gas-permeable function for removing dopants and oxide products while preventing direct thermal contact that causes stress-induced dislocations and slips in the wafer.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The support structure is segmented into two distinct functional components: the porous susceptor base that handles gas permeability and contaminant removal, and the ring structure that provides thermal buffering. This segmentation allows each component to optimize its specific function without compromising the other, resolving the contradiction between contaminant removal and stress prevention.

Inventive Principle:
Principle #1Segmentation

2Productivity

If high pretreatment and deposition temperatures are used, then deposition efficiency is improved, but stress-induced defects and autodoping increase

Engineering Contradiction:
Improvedeposition efficiencyVSAvoidstress-induced defects
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The ring structure serves as a thermal buffer that decouples the high temperature deposition process from the wafer, allowing high deposition temperatures to be maintained for efficiency while the ring absorbs and distributes thermal stress, preventing stress-induced defects in the wafer.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Temperature

If direct contact between wafer and porous susceptor is maintained, then thermal equilibration is achieved, but nanotopography effects and stress occur on the wafer

Engineering Contradiction:
Improvethermal equilibrationVSAvoidnanotopography effects
Core Design Contradiction:
TemperatureVSManufacturing precision

Solution Approach 1:

The ring structure acts as a distributed thermal contact interface between the porous susceptor and the wafer edge. This intermediary maintains thermal equilibration by providing a larger contact area that distributes thermal loads uniformly, preventing the localized stress concentrations and nanotopography effects that occur with direct point-contact support.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution results in stress-free epitaxially coated semiconductor wafers with improved edge roll-off and local planarity, reduced defects, and effective removal of autodoping and halo effects, allowing for higher deposition temperatures and enhanced process efficiency.

Implementation Method 1

gaseous substances are delivered from a region over the backside of the semiconductor wafer by gas diffusion through the susceptor

Methodology Applied
Scientific EffectGas diffusion: Diffusion

Implementation Method 2

a ring, placed on the susceptor, which acts as a thermal buffer between the susceptor and the supported semiconductor wafer

Methodology Applied
Scientific EffectThermal buffering: Thermal Insulation

Implementation Method 3

applying an epitaxial layer onto their polished front sides by chemical vapor deposition at temperatures of 800-1200° C.

Methodology Applied
Scientific EffectChemical vapor deposition: Chemical Vapour Deposition

Implementation Method 4

deposition of an epitaxial layer on a polished semiconductor wafer

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS7838398B2Epitaxially coated semiconductor wafer and device and method for producing an epitaxially coated semiconductor wafer
Publication Date: 2010.11.23 SILTRONIC AG
  • US7838398B2 patent drawing
  • US7838398B2 patent drawing
  • US7838398B2 patent drawing

AI summary

In a method for producing epitaxially coated semiconductor wafers, a multiplicity of prepared, front side-polished semiconductor wafers are successively coated individually with an epitaxial layer on their polished front sides at temperatures of 800-1200° C. in a reactor, while supporting the prepared semiconductor wafer over a susceptor having a gas-permeable structure, on a ring placed on the susceptor which acts as a thermal buffer between the susceptor and the supported semiconductor wafer, the semiconductor wafer resting on the ring, and its backside facing but not contacting the susceptor, so that gaseous substances are delivered from a region over the backside of the semiconductor wafer by gas diffusion through the susceptor into a region over the backside of the susceptor, the semiconductor wafer contacting the ring only in an edge region of its backside, wherein no stresses measurable by means of photoelastic stress measurement (“SIRD”) occur in the semiconductor wafer.