Epitaxial Silicon Wafer With ≤75 nm Peripheral COP Size
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Solution Overview
Problem
Conventional silicon single crystals used for epitaxial silicon wafers prioritize productivity over crystal quality, leading to increased Crystal Originated Particles (COPs) and reduced Bulk Micro Defect (BMD) density, particularly in the peripheral region, which compromises the gettering capability and semiconductor device yields.
Innovation Solution
Control the size of Crystal Originated Particles (COPs) in the peripheral region of silicon wafers to 75 nm or less by optimizing the Czochralski method parameters, including pulling speed, temperature gradient, and magnetic field, ensuring uniform BMD density across the wafer surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the pulling speed of silicon single crystal is increased to improve productivity, then productivity is improved, but the average COP size increases and BMD density decreases particularly in the peripheral region
Solution Approach 1:
The patent applies local quality by differentiating the COP size control between central and peripheral regions. Specifically, it controls the average COP size in the peripheral region (within 5 mm from the outermost edge) to be 75 nm or less, while allowing the central region to have larger COP sizes. This regional differentiation allows the use of higher pulling speeds for productivity while maintaining sufficient BMD density in the peripheral region where uniformity is most critical for semiconductor device fabrication.
2Productivity
If the pulling speed is increased, then productivity is improved, but the gettering capability decreases due to reduced BMD density
Solution Approach 1:
The patent applies parameter changes by establishing specific quantitative thresholds for COP size (average COP size ≤ 75 nm in peripheral region) and pulling speed ranges that optimize both productivity and gettering capability. By controlling the average COP size in the peripheral region to 75 nm or less, the patent ensures sufficient BMD density (1×10^8/cm³ or more) for effective gettering of heavy metal impurities, while still allowing higher pulling speeds that improve productivity compared to conventional methods.
3Reliability
If the average COP size in peripheral region is reduced to maintain BMD density, then gettering capability is maintained, but productivity may be reduced due to lower pulling speed
Solution Approach 1:
The patent resolves this contradiction by applying local quality control - it specifically targets the peripheral region (within 5 mm from the outermost edge) for strict COP size control (≤ 75 nm) to maintain gettering capability, while allowing the central region to have more relaxed COP size requirements. This localized approach enables higher overall pulling speeds and improved productivity while ensuring sufficient BMD density where it is most needed for impurity gettering.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances the uniformity of BMD density distribution, maintaining high gettering capability and preventing decreases in BMD density, thereby improving semiconductor device yields.
Implementation Method 1
growing a silicon single crystal by using a Czochralski method
Implementation Method 2
oxygen precipitates (Bulk Micro Defects: BMD) are formed within the silicon wafer to capture the heavy metal impurities
Implementation Method 3
the gettering technique, which may be intrinsic gettering (IG), where oxygen precipitates (Bulk Micro Defects: BMD) are formed within the silicon wafer to capture the heavy metal impurities
Data Source
AI summary
An epitaxial silicon wafer comprises a silicon wafer in which the entire surface, excluding an edge region from the outermost edge to 2 mm inward, is a COP region, and an epitaxial silicon layer formed on the surface of the silicon wafer. The average COP size in the peripheral region, located within 5 mm inward from the outermost edge of the silicon wafer, is 75 nm or less.