Epitaxial Wafer Thickness-Impurity Correlation Control
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Solution Overview
Problem
Semiconductor epitaxial wafers face challenges in minimizing variations in avalanche breakdown voltage and on-resistance across devices due to in-plane distributions of impurity concentration and thickness, which affect device uniformity and yield.
Innovation Solution
Controlling the correlation between the in-plane distribution of thickness and impurity concentration in the semiconductor epitaxial layer to cancel out fluctuations, ensuring a positive correlation to reduce variations in device characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional epitaxial growth is used without controlling thickness-impurity correlation, then manufacturing process is simpler, but in-plane variations in device characteristics increase
Solution Approach 1:
The patent applies parameter changes by controlling the correlation between thickness distribution and impurity concentration distribution during epitaxial growth. Specifically, it adjusts growth conditions to achieve a positive correlation where regions with greater thickness also have higher impurity concentrations, thereby compensating for thickness variations and reducing in-plane variations in device characteristics such as breakdown voltage and on-resistance.
2Reliability
If large margins are used in design specifications to account for variations, then device reliability is improved, but productivity decreases due to lower yield
Solution Approach 1:
The patent applies homogeneity by reducing in-plane variations in device characteristics through controlled epitaxial growth. By achieving a positive correlation between thickness and impurity concentration distributions, the method produces more uniform device performance across the wafer, thereby improving yield without requiring excessive design margins.
3Manufacturing precision
If epitaxial growth conditions are controlled to achieve positive correlation between thickness and impurity concentration, then in-plane variations are reduced, but manufacturing process complexity increases
Solution Approach 1:
The patent applies parameter changes by systematically controlling epitaxial growth parameters to establish a positive correlation between thickness and impurity concentration. This involves adjusting growth conditions such as temperature, pressure, and gas flow rates to achieve the desired correlation, thereby reducing in-plane variations while maintaining manufacturability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively diminishes in-plane variations in device characteristics, such as breakdown voltage and on-resistance, allowing for more uniform device performance and reduced costs by minimizing the need for large margins in design specifications.
Implementation Method 1
a first conductivity type semiconductor epitaxial layer that is disposed on a principal surface of the semiconductor wafer
Data Source
AI summary
Variations in device characteristics in a plane parallel to the principal surface of a semiconductor wafer are suppressed. A semiconductor epitaxial wafer includes a semiconductor wafer and a first conductivity type semiconductor epitaxial layer that is disposed on a principal surface of the semiconductor wafer and contains a first conductivity type impurity, and the thickness distribution of the semiconductor epitaxial layer and the concentration distribution of the impurity in the semiconductor epitaxial layer have a positive correlation in a plane parallel to the principal surface of the semiconductor wafer.