Epitaxial Wafer Defect Inspection and Dicing Optimization
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Solution Overview
Problem
The production of high-definition micro light-emitting diode (LED) displays is hindered by defects in epitaxial wafers, leading to yield loss and increased costs due to stringent yield control requirements, especially when aiming for tight pixel pitches and large die sizes.
Innovation Solution
A method and system for inspecting epitaxial wafers to detect defects, optimizing a dicing scheme to position dies around defects, and transferring good dies to a target wafer to maximize yield, using techniques like optical and electrical inspection, and dicing methods such as mechanical or plasma dicing, to create a reconstituted wafer suitable for high-resolution displays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional dicing schemes are used on epitaxial wafers, then the manufacturing process is simple, but the number of usable dies is reduced due to defects
Solution Approach 1:
The patent performs defect inspection and dicing scheme optimization before the actual dicing process. By pre-mapping defects on the epitaxial wafer and calculating optimal die layouts that avoid defect regions, the system determines which dies will be usable before cutting occurs, thereby maximizing the number of good dies without adding complexity to the physical dicing operation
Solution Approach 2:
The patent implements a dynamic dicing scheme where die positions and orientations are adjusted based on the specific defect distribution pattern observed during inspection. Rather than using a fixed regular grid pattern, the system dynamically optimizes the dicing layout to navigate around defect clusters, ensuring maximum utilization of defect-free regions on each wafer
2Reliability
If stringent yield control is enforced to ensure quality, then the reliability of display devices is improved, but the manufacturing cost increases
Solution Approach 1:
The system performs preliminary defect inspection and classification before dicing, identifying and mapping all defect locations on the epitaxial wafer. This advance knowledge allows the dicing scheme to be optimized to exclude defect-containing regions, ensuring high yield quality without requiring expensive post-dicing inspection and sorting processes
Solution Approach 2:
The patent creates a digital replica or map of the defect distribution pattern on the epitaxial wafer. This defect map is then used to simulate and optimize multiple dicing scenarios virtually, allowing the selection of the optimal dicing scheme that maximizes good die yield without requiring physical trial-and-error approaches
3Area of moving object
If large die sizes are produced to meet FHD display requirements, then the display resolution is improved, but the impact of defects increases leading to lower yield
Solution Approach 1:
Before dicing large wafers into FHD-sized dies, the system inspects and maps all defect locations across the entire wafer surface. This preliminary defect characterization allows the optimization algorithm to determine the maximum number of large-sized good dies that can be extracted from each wafer by positioning die boundaries to avoid defect regions
Solution Approach 2:
The patent applies different quality requirements to different regions of the wafer based on local defect density. Regions with low defect density are designated for large FHD die production, while regions with high defect density are either avoided or used for smaller dies if applicable, thereby optimizing the overall yield of usable large-sized dies from each wafer
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases the number of usable dies from each epitaxial wafer, optimizing die placement to minimize defects, thereby enhancing the yield and cost-efficiency for high-definition microLED displays with tight pixel pitches.
Implementation Method 1
The method further comprises the step of inspecting the epitaxial wafer by optical and/or electrical techniques. Advantageously, the defects can be detected by optical techniques such as spectroscopic or microscopic techniques.
Implementation Method 2
dicing methods such as mechanical or plasma dicing
Data Source
Figure 1
Figure 2(a)~2(c)
Figure 3(a)~3(d)
AI summary
A method is provided to produce dies for a wafer reconstitution. The method comprises steps of inspecting an epitaxial wafer (901) to detect one or more defects, overlaying a dicing scheme (902) on the epitaxial wafer (901) with the detected defects, classifying the dies in the dicing scheme (902) as good dies (903) or bad dies (904), and dicing the good dies (903) and transferring the good dies (903) onto a carrier wafer or a target wafer to wafer reconstitution.