Epitaxial Semiconductor Wafer with Highly Doped Substrate Layer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor wafer production methods, such as the Czochralski and float zone methods, face limitations in increasing dopant concentrations without introducing dislocations, resulting in high substrate resistance values above 0.9 mOhmcm for large-diameter power semiconductor components.
Innovation Solution
A semiconductor wafer with an epitaxial layer and an n++ or p++ doped layer extending into the substrate, where the dopant concentration is increased through diffusion or implantation, reducing substrate resistivity by at least 20% and minimizing dislocations, and the substrate thickness is reduced to enhance epitaxial layer integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dopant concentration is increased in the substrate wafer using conventional methods (CZ or FZ), then electrical resistance decreases, but dislocations are formed that disrupt the single crystal structure
Solution Approach 1:
The substrate wafer is divided into two distinct regions: an upper epitaxial layer with lower dopant concentration (maintaining crystal integrity) and a lower highly doped region (n++ or p++ layer) with higher dopant concentration (reducing resistance). This segmentation allows each region to fulfill its specific function without compromising the other.
Solution Approach 2:
Different dopant concentrations are applied to different regions of the substrate wafer. The upper region maintains lower dopant concentration for crystal stability, while the lower region has high dopant concentration for low resistance. This local differentiation resolves the contradiction by optimizing each region for its specific purpose.
2Manufacturing precision
If the substrate wafer thickness is reduced to enhance epitaxial layer integration, then manufacturing precision improves, but mechanical strength decreases
Solution Approach 1:
The substrate wafer is structured as a composite with an upper epitaxial layer and a lower highly doped region. This composite structure provides both the thin profile needed for precise epitaxial integration and the mechanical strength required for handling, as the highly doped lower region can be engineered to provide structural support.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in semiconductor wafers with significantly lower resistivity, making them suitable for high-performance power electronic components like power transistors and MOSFETs, while maintaining crystal integrity and reducing dislocation issues.
Implementation Method 1
dopant atoms of the n type or p type are introduced into the substrate wafer through the front surface of the substrate wafer, the dopant concentration in a layer which extends from the front surface of the substrate wafer into the substrate wafer being increased from the level n+ or p+ to the level n++ or p++
Implementation Method 2
comprising a layer deposited epitaxially on the front surface of the substrate wafer
Data Source
AI summary
A semiconductor wafer is formed of a substrate wafer of single crystal silicon doped with dopant atoms of the n type or p type, with a front surface and a back surface, contains a layer deposited epitaxially on the front surface of the substrate wafer. The substrate wafer additionally includes an n++ or p++ doped layer, which extends from the front surface of the substrate wafer into the substrate wafer and has a defined thickness. The semiconductor wafer is produced by a process in which dopant atoms of the n type or p type are introduced into the substrate wafer through the front surface of the substrate wafer, the dopant concentration in a layer which extends from the front surface of the substrate wafer into the substrate wafer being increased from the level n+ or p+ to the level n++ or p++, and an epitaxial layer is then deposited on this layer.


