Epitaxially Coated Silicon Wafer Edge Quality Control

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Solution Overview

Problem

Existing methods for inspecting and processing the edges of silicon wafers are inadequate, leading to unreliable quality control and inability to detect small defects, which affects the production of high-quality epitaxially coated wafers.

Innovation Solution

An automated edge inspection method that includes high-resolution defect characterization and sorting, combined with a specific process for producing epitaxially coated silicon wafers with a polished edge and adjacent region, ensuring surface roughness of 0.1-1.5 nm RMS and variation of 1-10% within a 3 mm width, using a sequence of edge rounding, polishing, cleaning, defect examination, and epitaxial coating in a reactor with optimized gas distribution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If visual inspection under microscope is used for quality control, then quality check can be performed, but reliability is insufficient and small defects cannot be detected

Engineering Contradiction:
Improvedefect detection capabilityVSAvoidquality control reliability
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent replaces manual visual inspection with an automated optical inspection system that uses light sources and sensors to automatically detect defects. This substitution of mechanical/manual inspection with an automated optical system enables reliable detection of small defects and ensures consistent quality control without human error.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The inspection system creates optical copies or images of the wafer edge region and processes these copies to detect defects. By working with optical representations rather than direct visual inspection, the system can analyze edge quality with enhanced precision and reliability.

Inventive Principle:
Principle #26Copying

2Manufacturing precision

If edge polishing is performed to improve edge quality, then surface roughness is reduced, but manufacturing complexity increases

Engineering Contradiction:
Improveedge surface roughnessVSAvoidmanufacturing process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent performs preliminary edge rounding before the main polishing process. This preliminary action prepares the edge surface in advance, making the subsequent polishing process more effective and reducing the complexity of achieving the desired surface roughness. By pre-shaping the edge, the overall manufacturing process becomes more manageable.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The edge treatment process is divided into separate stages: edge rounding followed by edge polishing. This segmentation allows each process to be optimized independently, with rounding removing major irregularities and polishing achieving the final surface quality, thereby managing manufacturing complexity through process breakdown.

Inventive Principle:
Principle #1Segmentation

3Measurement precision

If inspection apparatus is used to examine wafer edge, then defect detection is enabled, but edge exclusion zone of 3 mm cannot be inspected

Engineering Contradiction:
Improvedefect detection capabilityVSAvoidinspectable area
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent uses optical imaging to create a two-dimensional representation of the three-dimensional wafer edge region. This dimensional transformation allows the inspection system to capture and analyze the entire edge circumference including the previously inaccessible 3 mm exclusion zone, effectively extending the inspectable area beyond physical contact limitations.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method ensures improved edge quality, reduces defects, and optimizes the fabrication process by providing epitaxially coated silicon wafers with low roughness and reliable defect detection, enhancing the production of high-quality wafers.

Implementation Method 1

epitaxially coated silicon wafer

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Implementation Method 2

in a second step, an etching medium with a flow rate of 0.5-5 slm is added to the hydrogen atmosphere and is distributed in the reactor chamber by means of a gas distribution device

Methodology Applied
Scientific EffectChemical vapor deposition: Chemical Vapour Deposition

Implementation Method 3

the edge of a centrally rotating silicon wafer is pressed against a centrally rotating polishing drum with a specific force (contact pressure). U.S. Pat. No. 5,989,105 discloses an edge polishing method of this type, in which the polishing drum consists of an aluminum alloy and is covered with a polishing cloth

Methodology Applied
Scientific EffectAbrasion: Abrasion

Implementation Method 4

in a first step, a treatment in a hydrogen atmosphere at a flow rate of 1-100 slm is effected and, in addition, in a second step, an etching medium with a flow rate of 0.5-5 slm is added to the hydrogen atmosphere

Methodology Applied
Scientific EffectChemical etching:

Data Source

PatentUS8304860B2Epitaxially coated silicon wafer and method for producing an epitaxially coated silicon wafer
Publication Date: 2012.11.06 SILTRONIC AG
  • US8304860B2 patent drawing
  • US8304860B2 patent drawing
  • US8304860B2 patent drawing

AI summary

Epitaxially coated silicon wafers have a rounded and polished edge region and a region adjacent to the edge having a width of 3 mm on the front and rear sides, a surface roughness in edge region of 0.1-1.5 nm RMS relative to a spatial wavelength range of 10-80 μm, and a variation of surface roughness of 1-10%. The wafer edges, after polishing, are examined for defects and roughness at the edge and surrounding region. Silicon wafers having a surface roughness of less than 1 nm RMS are pretreated in single wafer epitaxy reactors, first in a hydrogen atmosphere at a flow rate of 1-100 slm and in a second step, an etching medium with a flow rate of 0.5-5 slm is conducted onto the edge region of the wafer by a gas distribution device. The wafer is then epitaxially coated.