Epitaxial Wafer Polishing Control for Predictive Flatness Compensation
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Solution Overview
Problem
Existing methods for producing epitaxial wafers fail to effectively control flatness, leading to unacceptable parameters and yield loss due to uneven thickness distribution and mismatch between the polished wafer surface profile and the deposited epitaxial layer, which are not identified until irreversible processing has occurred.
Innovation Solution
A method involving measuring epitaxial wafers to determine deposition layer profiles, polishing semiconductor wafers to assess surface profiles, and adjusting polishing process conditions based on predicted post-epitaxy parameters to ensure compliance with specifications, thereby controlling wafer flatness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If polishing processes are used to improve flatness and parallelism of substrate wafers, then surface flatness is improved, but edge roll-off occurs reducing the portion of the wafer available for device fabrication
Solution Approach 1:
The patent applies parameter changes by adjusting polishing process conditions (pressure, speed, slurry flow rate, temperature) to control the removal rate and achieve a desired surface profile that maintains flatness while minimizing edge roll-off. By changing these parameters, the polishing process can be optimized to produce a thickness profile that compensates for edge effects during epitaxial growth.
2Manufacturing precision
If epitaxial process conditions are adjusted to provide uniform growth rates, then epitaxial layer uniformity is improved, but process complexity increases
Solution Approach 1:
The patent applies preliminary action by performing measurements and predictions before the epitaxial process to determine the appropriate substrate thickness profile. By calculating the required compensation in advance based on measured deposition layer profiles from previous runs, the process conditions can be pre-adjusted to achieve uniform growth without requiring complex real-time control during epitaxy.
Solution Approach 2:
The patent implements feedback by measuring the deposition layer profile from previous epitaxial runs and using this information to adjust substrate thickness or polishing parameters for subsequent runs. This closed-loop approach allows the system to self-correct and maintain uniform epitaxial layer thickness without increasing the complexity of the epitaxial process itself.
3Area of stationary object
If polishing process conditions are adjusted to minimize edge roll-off, then usable wafer area is improved, but surface flatness may deteriorate
Solution Approach 1:
The patent uses parameter changes by adjusting multiple polishing parameters simultaneously (pressure distribution, rotational speed, slurry flow) to achieve a balance between maintaining surface flatness and minimizing edge roll-off. The system can modify these parameters to produce a specific thickness profile that compensates for edge effects while preserving overall flatness.
Solution Approach 2:
The patent applies local quality by allowing different regions of the wafer to have different thickness characteristics. The polishing process can be controlled to create a non-uniform thickness profile where the center and edge regions have optimized characteristics - the center maintains flatness while the edge has reduced roll-off, accepting that different parts of the wafer have different properties.
4Productivity
If yield loss is reduced through predictive control, then productivity is improved, but measurement and prediction capabilities must be enhanced
Solution Approach 1:
The patent applies preliminary action by measuring substrate and deposition layer profiles before and after epitaxial growth to predict the final epitaxial wafer flatness. This early prediction allows yield issues to be identified and corrected before irreversible processing completes, reducing scrap without requiring excessively complex measurement systems.
Solution Approach 2:
The patent uses copying by creating a predicted model of the post-epitaxy wafer profile based on measurements of the substrate and deposition layer. This predictive model allows the system to estimate final flatness parameters without directly measuring the finished product, reducing the need for high-precision final measurement equipment while still maintaining high yield.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the production of epitaxial wafers by reducing yield loss and improving flatness control through predictive adjustments, ensuring compliance with specifications before irreversible processing.
Implementation Method 1
Grinding and polishing processes are commonly used to improve flatness and parallelism of the front and back surfaces of the substrate wafer after the wafer is cut from an ingot
Implementation Method 2
polishing processes may cause the profile of the substrate wafer to change near the edge of the wafer due to an uneven distribution of mechanical and/or chemical forces near the edge
Implementation Method 3
epitaxial chemical vapor deposition (CVD) is a process for forming epitaxial wafers and involves growing a thin layer of material on a polished semiconductor wafer so that the lattice structure is identical to that of the wafer
Implementation Method 4
A susceptor, which supports the polished wafer in the deposition chamber during the epitaxial deposition, is rotated during the process to allow the epitaxial layer to grow evenly
Implementation Method 5
During epitaxial CVD, a polished semiconductor wafer may be heated to a suitable temperature in a deposition chamber of an epitaxial reactor
Data Source
AI summary
A method of producing an epitaxial semiconductor wafer includes measuring one or more epitaxial semiconductor wafers to determine an epitaxial deposition layer profile produced by an epitaxy apparatus. The method also includes polishing a semiconductor wafer using a polishing assembly and measuring the polished semiconductor wafer to determine a surface profile of the polished wafer. The method further includes generating a predicted post-epitaxy surface profile of the polished wafer by comparing the surface profile of the polished wafer and the determined epitaxial deposition layer profile produced by the epitaxy apparatus. The method also includes determining a predicted post-epitaxy parameter based on the predicted post-epitaxy surface profile and adjusting, based on the predicted post-epitaxy parameter, a process condition of the polishing assembly.