Epitaxial Wafer Flatness Control Through Predictive Polishing
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Solution Overview
Problem
Existing methods for producing epitaxial wafers struggle to maintain controlled flatness, leading to unacceptable parameters and yield loss due to uneven thickness distribution and edge roll-off, which are not corrected until irreversible processing occurs.
Innovation Solution
A system comprising a polishing assembly, measuring device, and computer system that measures and adjusts process conditions to predict and control the flatness of epitaxial wafers by comparing surface profiles and thickness profiles before and after epitaxial deposition, allowing for real-time adjustments to ensure compliance with specifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If polishing processes are used to improve flatness and parallelism of substrate wafers, then surface flatness is improved, but edge roll-off occurs reducing the portion of the wafer available for device fabrication
Solution Approach 1:
The patent applies preliminary action by measuring the surface profile of the substrate wafer before epitaxial deposition and using this measurement to predict the post-epitaxy surface profile. This allows edge roll-off to be compensated for in advance by adjusting polishing parameters or selecting appropriate substrate wafers, ensuring that the final epitaxial wafer meets flatness specifications while maximizing usable area.
2Ease of manufacture
If epitaxial processes are performed to grow epitaxial layers, then device fabrication capability is enabled, but uniformity of epitaxial growth rates across the wafer surface is affected by temperature gradients and gas flow causing uneven thickness distribution
Solution Approach 1:
The patent implements feedback by measuring the surface profile of substrate wafers before epitaxial deposition, predicting the post-epitaxy surface profile based on the measured profile and epitaxial growth characteristics, and using this prediction to adjust polishing parameters or select appropriate substrate wafers. This closed-loop approach compensates for temperature gradients and gas flow non-uniformities during epitaxial growth, ensuring uniform epitaxial layer thickness while maintaining device fabrication capability.
3Manufacturing precision
If process conditions during polishing and epitaxy are adjusted to optimize surface profile, then flatness is improved, but adjustments are made independently for each step without considering the combined effect, leading to unacceptable yield
Solution Approach 1:
The patent merges the polishing and epitaxial process considerations by measuring the substrate wafer surface profile before epitaxy, predicting the combined effect of polishing and epitaxial growth on the final surface profile, and making coordinated adjustments to polishing parameters based on this prediction. This integrated approach ensures that both polishing and epitaxial processes work together to achieve the desired flatness, maximizing yield by preventing defects that would otherwise require scrapping wafers after irreversible epitaxial processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the production of epitaxial wafers by improving yield and reducing scrap rates through precise control of flatness parameters, ensuring compliance with specifications before irreversible processing.
Implementation Method 1
measuring device, where the computer system is in communication with the polishing assembly and the measuring device
Implementation Method 2
epitaxial chemical vapor deposition (CVD) is a process for forming epitaxial wafers and involves growing a thin layer of material on a polished semiconductor wafer
Data Source
AI summary
A system for controlling flatness of an epitaxial semiconductor wafer includes a polishing assembly, a measuring device, and a computer system in communication with the polishing assembly and the measuring device. The computer system stores and executes instructions that cause the computer system to measure one or more epitaxial semiconductor wafers to determine an epitaxial deposition layer profile produced by an epitaxy apparatus, polish a semiconductor wafer using a polishing assembly and measure the polished semiconductor wafer to determine a surface profile of the polished wafer, generate a predicted post-epitaxy surface profile of the polished wafer by comparing the surface profile of the polished wafer and the determined epitaxial deposition layer profile produced by the epitaxy apparatus, determine a predicted post-epitaxy parameter based on the predicted post-epitaxy surface profile and adjust, based on the predicted post-epitaxy parameter, a process condition of the polishing assembly.