Epitaxial Wafer Thickness Profile for Lower Heteroepitaxial Defects
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Solution Overview
Problem
Conventional heteroepitaxial growth on silicon wafers leads to excessive stress, causing stacking faults and threading dislocations due to lattice constant differences, and is prone to auto-doping issues from dopant diffusion.
Innovation Solution
An epitaxial wafer design with a semiconductor film thickness less than 1 at the outer-peripheral portion compared to the center, reducing defects such as stacking faults and threading dislocations, using a silicon substrate with a film thickness distribution that minimizes lattice relaxation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If heteroepitaxial growth is performed on a silicon wafer, then semiconductor materials other than silicon can be formed, but stress attributed to lattice constant difference causes stacking faults and threading dislocations
Solution Approach 1:
The patent applies local quality by creating a buffer layer with gradually changing composition between the silicon substrate and the target semiconductor layer. This buffer layer has different properties at different depths, with the composition transitioning from silicon-rich at the substrate interface to target-material-rich at the epitaxial interface, thereby locally managing stress distribution to reduce defects
Solution Approach 2:
The patent uses composite materials by forming a buffer layer that is a mixture of silicon and the target semiconductor material. This composite structure allows gradual lattice constant transition, reducing the abrupt stress that would otherwise cause stacking faults and threading dislocations at the heteroepitaxial interface
2Stress or pressure
If a low-resistance silicon wafer with high concentration dopant is used, then stress can be suppressed, but auto-doping due to outward diffusion of dopant occurs
Solution Approach 1:
The patent extracts the stress management function from the dopant-containing silicon substrate by introducing a separate buffer layer. This buffer layer specifically addresses stress relief through compositional gradient without introducing dopants, thereby separating the stress management function from the substrate and preventing auto-doping issues
Solution Approach 2:
The buffer layer acts as an intermediary between the silicon substrate and the target semiconductor layer. It mediates the lattice mismatch and stress without requiring high-concentration dopants, providing a clean interface that prevents unwanted dopant diffusion while still achieving stress suppression
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design significantly reduces defects, achieving excellent quality and reliability in heteroepitaxial wafers suitable for cutting-edge devices by minimizing stress-induced defects.
Implementation Method 1
stress attributed to a difference in lattice constant between silicon and an epitaxial film is applied thereto, and excessive stress results in problems of triggering stacking faults or threading dislocations
Data Source
AI summary
The present invention is an epitaxial wafer, including an epitaxial film of a semiconductor material different from silicon being formed on a silicon substrate, in which the epitaxial film has a film thickness of less than 1 at a wafer outer-peripheral portion when a film thickness at a center of the wafer is defined as 1. Thereby, the epitaxial wafer having a heteroepitaxial film with few defects without dependence on a dopant concentration or a variety of a silicon wafer is provided.