Epitaxy-Everywhere Backside Contacts Without Bottom Dielectric Isolation
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Solution Overview
Problem
Semiconductor devices with bottom dielectric isolation face issues such as exposure of source/drain regions to damage and non-uniform epitaxy growth due to pinholes, affecting the quality of the source/drain regions during backside contact processing.
Innovation Solution
The implementation of self-aligned direct backside contacts using epitaxy everywhere under the source/drain regions, where epitaxial contact placeholders and self-aligned direct backside contacts are embedded in the backside interlayer dielectric, ensuring uniform and high-quality epitaxy growth without the need for bottom dielectric isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bottom dielectric isolation is used to protect source/drain regions, then source/drain regions are protected during backside contact processing, but defects such as pin holes in the dielectric layer expose source/drain regions to damage and impact epitaxy growth uniformity
Solution Approach 1:
The patent removes the bottom dielectric isolation layer entirely, extracting the problematic element that caused both protection failures (pin holes) and epitaxy growth issues. Instead of using a dielectric layer, the invention directly forms backside contacts to the substrate, eliminating the intermediate layer that compromised both protection and uniformity.
Solution Approach 2:
The patent performs preliminary protection by forming a protective layer on the front side of the substrate before backside contact processing. This advance protective measure ensures source/drain region protection during backside processing without requiring a bottom dielectric isolation layer, thus maintaining both reliability and epitaxy growth uniformity.
2Manufacturing precision
If bottom dielectric isolation is removed to enable uniform epitaxy growth, then epitaxy growth uniformity is improved, but source/drain regions become exposed to potential damage during backside contact processing
Solution Approach 1:
The patent introduces a protective layer as an intermediary element on the front side of the substrate. This protective layer serves as a mediator that provides source/drain region protection during backside contact processing without interfering with epitaxy growth, thus maintaining both reliability and manufacturing precision.
Solution Approach 2:
The protective layer is formed in advance before backside contact processing, providing preliminary protection to source/drain regions. This advance preparation ensures that when the backside is processed, the source/drain regions are already protected, eliminating the need for bottom dielectric isolation while maintaining both protection and uniformity.
3Reliability
If bottom dielectric isolation is used, then source/drain regions are protected during backside contact processing, but the presence of dielectric impacts epitaxy growth behavior and uniformity
Solution Approach 1:
The patent extracts and removes the bottom dielectric isolation layer that was causing epitaxy growth problems. By eliminating this intermediate layer, the invention allows direct epitaxy growth on the substrate, improving ease of manufacture and epitaxy growth behavior while maintaining protection through alternative means (front-side protective layer).
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach protects the source/drain regions during backside contact processing and achieves uniform, high-quality epitaxy, minimizing defects and ensuring reliable semiconductor device performance.
Implementation Method 1
growing a shallow epitaxial contact placeholder in the first trench and a deep epitaxial contact placeholder in the second trench
Data Source
AI summary
Self-aligned direct backside contacts by an epitaxy everywhere under source/drain region approach are provided. In one aspect, a semiconductor device includes: a field-effect transistor(s) on a backside interlayer dielectric; an epitaxial contact placeholder in the backside interlayer dielectric that directly contacts a first source/drain region of the field-effect transistor(s); and a self-aligned direct backside contact in the backside interlayer dielectric that directly contacts a second source/drain region of the field-effect transistor(s). The epitaxial contact placeholder extends a distance d1 into the backside interlayer dielectric from the first source/drain region, and the self-aligned direct backside contact extends a distance d2 into the backside interlayer dielectric from the second source/drain region, where d2>d1. The field-effect transistor(s) can include a stack of active layers surrounded by a gate, and the first/second source/drain regions on opposite sides thereof. A method of fabricating the present semiconductor device is also provided.