Epitaxy Level Packaging for Heterogeneous Integration
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Solution Overview
Problem
Current heterogeneous integration technologies face challenges in accommodating dissimilar material systems, requiring costly customized processes and limiting the use of low-cost foundries, and struggle with complex assembly and lattice engineering, which increases costs and reduces efficiency.
Innovation Solution
The development of epitaxy-level packaging (ELP) technology, which involves arranging pieces of compound semiconductor wafers into an assembly pattern on a larger assembly substrate with through-substrate vias to form epitaxial layers, allowing for the integration of multiple types of compound semiconductor materials on a single substrate, using existing wafer fabrication processes and reducing the complexity of assembly and lattice engineering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If heterogeneous integration of dissimilar material systems is performed using conventional technologies, then diverse semiconductor materials can be integrated, but costly customized processes are required and low-cost foundries cannot be used
Solution Approach 1:
The patent introduces an intermediary substrate that mediates between dissimilar semiconductor materials. This substrate serves as a common platform that can accommodate different material systems (e.g., GaAs, GaN, Si) with different lattice structures and thermal properties, enabling heterogeneous integration without requiring customized processing for each material pair.
Solution Approach 2:
The integration process is segmented into independent stages: substrate preparation, separate device fabrication on individual substrates, and subsequent assembly on the intermediary substrate. This segmentation allows each material system to be processed using its optimized conventional processes, then integrated without requiring costly customized joint processing.
2Adaptability or versatility
If complex assembly and lattice engineering are used for heterogeneous integration, then diverse materials can be integrated, but costs increase and efficiency decreases
Solution Approach 1:
The patent performs preliminary actions by preparing standardized substrates with pre-defined structures and properties before device fabrication. These pre-prepared substrates include appropriate buffer layers, lattice-matched structures, and thermal management features, eliminating the need for complex lattice engineering during the integration phase and significantly improving efficiency.
3Adaptability or versatility
If conventional heterogeneous integration methods are used, then multiple chips can be integrated, but assembly complexity increases
Solution Approach 1:
The intermediary substrate is designed with universal features that can accommodate multiple types of semiconductor devices and interconnection methods. It provides standardized mounting structures, electrical interconnection interfaces, and thermal management capabilities that work across different material systems, simplifying the assembly process by providing a unified platform for diverse components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
ELP technology enables efficient heterogeneous integration by standardizing wafer sizes, reducing manufacturing and material costs, and enhancing device miniaturization, reliability, and yield, while allowing for the integration of diverse semiconductor materials on a single platform, thus overcoming the limitations of conventional techniques.
Implementation Method 1
An epitaxial layer is then formed in the assembly substrate within the plurality of through substrate vias with an epitaxial process
Data Source
AI summary
A method of growth and transfer of epitaxial structures from semiconductor crystalline substrate(s) to an assembly substrate. Using this method, the assembly substrate encloses one or more semiconductor materials and defines a wafer size that is equal to or larger than the semiconductor crystalline substrate for further wafer processing. The process also provides a unique platform for heterogeneous integration of diverse material systems and device technologies onto one single substrate.


