Source/Drain Epitaxy Merge Control Using Fin Spacer Heights

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Solution Overview

Problem

Existing FinFET manufacturing methods struggle to selectively merge or separate epitaxy regions for different circuit types, such as logic and SRAM circuits, due to simultaneous epitaxy processes, leading to increased complexity and manufacturing costs.

Innovation Solution

A flexible merge scheme is implemented by adjusting the heights of fin spacers in different device regions through controlled etching processes, allowing for independent control of epitaxy region formation, enabling merged or un-merged source/drain regions based on circuit requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If simultaneous epitaxy is performed for different regions to save manufacturing cost, then manufacturing cost is reduced, but selective control of merged or separated epitaxy regions for different circuits is lost

Engineering Contradiction:
Improvemanufacturing costVSAvoidselective control of epitaxy regions
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The device region is divided into first and second device regions with different fin spacer heights. This segmentation allows independent control of epitaxy region merging behavior in each region, enabling selective merged or separated epitaxy regions for different circuit types while maintaining a common epitaxy process

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different fin spacer heights are applied to different device regions to create local variations in epitaxy control. The first device region has fin spacers of a first height enabling merged epitaxy regions, while the second device region has fin spacers of a second height enabling separated epitaxy regions

Inventive Principle:
Principle #3Local quality

2Adaptability or versatility

If fin spacer heights are adjusted to control epitaxy region merging, then selective control for different circuits is achieved, but process complexity increases

Engineering Contradiction:
Improveselective control of epitaxy regionsVSAvoidprocess complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The formation of fin spacers with different heights is combined into a single integrated process flow. Fin spacers are formed in both device regions through coordinated etching processes, and a common epitaxy process is then applied to both regions, achieving selective control without requiring separate epitaxy processes

Inventive Principle:
Principle #5Merging (Combining)

3Adaptability or versatility

If trimmed etching is used to separate merged epitaxy regions, then separation for SRAM circuits is achieved, but manufacturing complexity and cost increase

Engineering Contradiction:
Improveseparation of epitaxy regionsVSAvoidmanufacturing complexity
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The fin spacer heights are predetermined during the spacer formation process to pre-establish the merging or separating behavior of epitaxy regions. This preliminary action eliminates the need for subsequent trimmed etching processes to achieve separation, as the separation is already built into the structure before epitaxy

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces manufacturing costs by using a common deposition process for fin spacers and epitaxy, while achieving tailored FinFET designs that meet the specific requirements of various circuits, enhancing production efficiency and device performance.

Implementation Method 1

portions of the epitaxial regions grown from the neighboring fins are merged, and the portions of the other epitaxial regions grown from the other neighboring fins are separated from each other

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS12408315B2Flexible merge scheme for source/drain epitaxy regions
Publication Date: 2025.09.02 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12408315B2 patent drawing
  • US12408315B2 patent drawing
  • US12408315B2 patent drawing

AI summary

A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.