Local Epitaxy Nanofilms for GAA Nanowire Stack Alignment
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Solution Overview
Problem
The formation of epitaxy layers within a trench can be compromised by facet edge portions, leading to inferior epitaxy growth and quality issues, particularly due to the angled facet edges affecting the thickness and alignment of subsequent epitaxy layers, which in turn impacts the performance of nanowire stack-based gate-all-around (GAA) transistors.
Innovation Solution
The technique involves forming epitaxy layers within a trench with angled recesses on the sidewall, where the sizes of the recesses control the thickness of the epitaxy layers, and using cap layers to prevent vertical growth beyond the exposed recesses, ensuring the facet edge portions are aligned and extending substantially flat throughout the trench, with dynamic feedback control for precise thickness optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If epitaxy layers are formed within a trench with angled sidewalls, then the trench can be filled and subsequent layers can be formed, but the facet edge portions cause inferior epitaxy growth and quality issues
Solution Approach 1:
The patent applies preliminary action by forming recesses in the trench sidewalls before epitaxy layer deposition. These pre-formed recesses serve as guides to direct the facet edges of epitaxy layers into predetermined positions, preventing the harmful facet edge portions from compromising subsequent epitaxy growth. The recesses are created through selective etching of the trench sidewalls at specific locations before the epitaxy process begins.
Solution Approach 2:
The patent introduces recesses as intermediary structures that mediate between the angled trench sidewalls and the epitaxy layers. These recesses act as intermediate features that capture and redirect the facet edges, serving as a buffer zone that prevents direct contact between harmful facet edges and the growth interface of subsequent epitaxy layers.
2Ease of manufacture
If the thickness of epitaxy layers is controlled by the trench geometry, then the growth can be simplified, but the accuracy of thickness control is insufficient
Solution Approach 1:
The patent implements feedback control by monitoring the thickness of epitaxy layers during the deposition process and adjusting growth parameters in real-time. Sensors detect the actual thickness being formed, and this information feeds back to the epitaxy system to modify deposition rates, ensuring the final thickness matches the target specification with high precision.
Solution Approach 2:
The patent uses pre-formed recesses with predetermined depths and geometries as physical references for thickness control. The recess dimensions are designed in advance to correspond to the desired epitaxy layer thickness, providing a built-in mechanical stop and reference feature that guides the epitaxy growth to the correct thickness without requiring complex real-time adjustments.
3Speed
If gate lengths are scaled down to achieve faster switching speed, then the drive current increases, but short-channel effects compromise the current control function
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional nanowire stacks with gate-all-around configuration. By stacking multiple nanowires vertically and surrounding them with gates on all sides (top, bottom, and sidewalls), the invention creates a 3D structure that enhances electrostatic control over the channel, effectively suppressing short-channel effects while maintaining scaled dimensions for high-speed operation.
Solution Approach 2:
The patent employs composite material structures consisting of alternating layers of different semiconductor materials (e.g., Si/SiGe) in the nanowire stack. These composite structures provide both mechanical stability and optimized electrical properties, with different materials contributing specific characteristics such as strain engineering for carrier mobility enhancement and bandgap engineering for device performance optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the quality and accuracy of epitaxy layers, resulting in optimized nanowire stacks for GAA transistors, improving electrostatic control and reducing short-channel effects, thereby enhancing the performance and reliability of integrated circuits.
Implementation Method 1
Local epitaxy nanofilms for nanowire stack GAA device
Data Source
AI summary
The disclosed technique forms epitaxy layers locally within a trench having angled recesses stacked in the sidewall of the trench. The sizes of the recesses are controlled to control the thickness of the epitaxy layers to be formed within the trench. The recesses are covered by cap layers and exposed one by one sequentially beginning from the lowest recess. The epitaxy layers are formed one by one within the trench with the facet edge portion thereof aligned into the respective recess, which is the recess sequentially exposed for the epitaxy layer.