Epitaxy Temperature Ramping with Edge Offset Control
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Solution Overview
Problem
Conventional semiconductor production systems face challenges in balancing processing time and defect formation, particularly with crystallographic slip and auto-doping, during high-temperature epitaxial silicon deposition, where large temperature differences and slow ramping rates are necessary but result in lengthy processing times and product degradation.
Innovation Solution
The method involves measuring and controlling substrate temperatures at multiple locations using pyrometers to implement a multi-step temperature ramping process with varying rates, including fast and slow ramps, and maintaining specific temperature gradients to minimize defects, while also controlling cooling rates to prevent thermal stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If slow temperature ramping rates are used to reduce crystallographic slip defects, then manufacturing precision is improved, but productivity deteriorates due to lengthy processing times
Solution Approach 1:
The temperature ramping process is divided into multiple segments with different heating rates. A first temperature ramping step uses a faster rate (e.g., 10-50°C/minute) to quickly reach intermediate temperature, followed by a second step using a slower rate (e.g., 1-5°C/minute) to reach final processing temperature. This segmentation allows the system to benefit from both fast and slow ramping phases, reducing total processing time while maintaining crystal quality.
Solution Approach 2:
The heating rate parameter is dynamically changed during the temperature ramping process. The system transitions from a higher heating rate in the first temperature ramping step to a lower heating rate in the second step. This parameter change enables the process to achieve both speed and precision by adapting the heating rate to the specific temperature range and crystal growth stage.
2Productivity
If large temperature differences are applied during epitaxial growth, then productivity is improved through faster processing, but manufacturing precision deteriorates due to increased thermal stress and crystal defects
Solution Approach 1:
The temperature gradient across the substrate is dynamically controlled during the epitaxial growth process. The system adjusts heating zones to maintain optimal temperature distribution, preventing excessive thermal stress that would compromise crystal quality while enabling faster overall processing through controlled temperature differences.
3Productivity
If fast temperature ramping rates are used to reduce processing time, then productivity is improved, but manufacturing precision deteriorates due to increased crystallographic slip defects
Solution Approach 1:
The temperature ramping process is divided into multiple segments with different heating rates. A first temperature ramping step uses a faster rate (e.g., 10-50°C/minute) to quickly reach intermediate temperature, followed by a second step using a slower rate (e.g., 1-5°C/minute) to reach final processing temperature. This segmentation allows the system to benefit from both fast and slow ramping phases, reducing total processing time while maintaining crystal quality.
Solution Approach 2:
The heating rate parameter is dynamically changed during the temperature ramping process. The system transitions from a higher heating rate in the first temperature ramping step to a lower heating rate in the second step. This parameter change enables the process to achieve both speed and precision by adapting the heating rate to the specific temperature range and crystal growth stage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables faster processing times with reduced crystallographic slip and auto-doping effects, achieving high-quality epitaxial silicon layers by maintaining uniform temperature gradients and preventing thermal stress during deposition and cooling.
Implementation Method 1
measuring a center substrate temperature using a first pyrometer configured to optically measure temperature of the substrate
Implementation Method 2
an upper heater element array supported above the upper wall of the chamber body
Implementation Method 3
heating the substrate to a desired deposition temperature
Data Source
AI summary
Substrate processing systems and methods include: (a) seating a substrate on a support; (b) optically measuring center substrate temperature using a first pyrometer; (c) optically measuring edge substrate temperature using a second pyrometer; and (d) determining an edge offset temperature between the edge substrate temperature and the center substrate temperature. Three temperature ramping steps are used to heat up the substrate for processing: two fast ramping steps and one slow ramping steps. After substrate processing, an initial, controlled cooling step is provided. During at least the second fast temperature ramping step, the slow temperature ramping step, the substrate processing step(s), and the initial controlled cooling step, heating of the substrate is controlled to place and/or hold the edge offset temperature within predetermined ranges in order to maintain uniform temperature and/or a desired temperature gradient across the substrate. Such systems and methods help avoid crystal defects (e.g., slip) and/or auto-doping.