Semiconductor Wafer Epitaxy Temperature Control via Recessed Test Structures
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Solution Overview
Problem
Current epitaxial processes lack inline temperature measurement, leading to temperature fluctuations that result in vertical and horizontal dimension deviations of epitaxial structures outside specified ranges, causing wafer scrapping and alignment issues in subsequent photolithography processes.
Innovation Solution
A method where recessed test structures are formed on semiconductor wafers before epitaxy, with dimensions measured before and after epitaxial growth to determine deviations, allowing for temperature adjustments in the processing chamber to maintain process specifications, thereby preventing wafer wastage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If no inline temperature measurement is performed during epitaxial process, then the measurement system remains simple, but temperature fluctuations cause dimension deviations outside specified ranges leading to wafer scrapping
Solution Approach 1:
A test structure is introduced as an intermediary element that indirectly reflects temperature conditions through its dimensional changes. Instead of directly measuring temperature, the patent uses the test structure's dimension as a mediator to infer process temperature and detect deviations, thereby achieving precise process control without complex temperature measurement systems.
Solution Approach 2:
The patent replaces direct thermal measurement with a mechanical/dimensional measurement approach. By measuring the dimension of the test structure (a mechanical property) instead of directly measuring temperature (a thermal property), the system achieves process monitoring through dimensional changes that correlate with temperature variations.
2Productivity
If temperature is not monitored during epitaxial process, then processing continues without interruption, but temperature deviations are not detected until after process completion causing wafer wastage
Solution Approach 1:
A test structure is formed preliminarily on the wafer before the main epitaxial process. This test structure serves as an early indicator that will reveal temperature deviations during or after processing, allowing detection of process issues before they affect the entire wafer batch and causing wastage.
Solution Approach 2:
The patent implements a feedback mechanism where the dimension of the test structure is measured and compared against expected values. This feedback information is used to detect temperature deviations and adjust subsequent processing, ensuring continuous process control and preventing wafer scrapping.
3Adaptability or versatility
If temperature variance exceeds ±5°C during epitaxial process, then processing is faster and more flexible, but alignment performance and sheet resistance fall outside specified ranges
Solution Approach 1:
The patent replaces direct temperature control and measurement with a dimensional measurement approach. By measuring the test structure's dimension (a mechanical property) that correlates with temperature effects, the system maintains process flexibility while ensuring alignment precision through indirect temperature monitoring.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method ensures that subsequent lots of wafers are processed at the correct temperature, reducing wastage and maintaining alignment accuracy by adjusting the epitaxial process temperature based on measured deviations from predetermined limits.
Implementation Method 1
an epitaxial structure grown above the recessed test structure in the epitaxy step
Data Source
Figure 1~2
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Figure 8~12
AI summary
A method of processing semiconductor wafers comprises forming a pattern of recesses in an exposed surface of each wafer in a lot, prior to an epitaxy step. At least one recessed test structure is included in the pattern of recesses. At least one dimension of the recessed test structure is determined prior to the epitaxy step, then a corresponding dimension of an epitaxial structure grown above the recessed test structure in the epitaxy step is measured. A deviation between the dimension of the recessed test structure and the dimension of the epitaxial structure is determined and, from the deviation, the process temperature at which the epitaxy step was performed is determined. In case the deviation exceeds a predetermined limit, the temperature in the process chamber is adjusted for a subsequent lot of wafers to be processed.