EPROM Cell Array Area Reduction via Local Block Selectors

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Solution Overview

Problem

Existing EPROM cell arrays require a large area due to the need for a selection transistor for each unit cell, which increases the area significantly.

Innovation Solution

The EPROM cell array design eliminates the need for a selection transistor by using a configuration where unit cells are electrically coupled to common selection lines, allowing program and read operations to be performed without a selection transistor, thereby reducing the array's area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a selection transistor is used for each unit cell, then the reliability of cell selection is improved, but the area of the EPROM cell array increases significantly

Engineering Contradiction:

Improvecell selection reliabilityVSAvoidEPROM cell array area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent extracts and removes the selection transistor from each unit cell configuration. Instead of having a selection transistor for every unit cell, the design eliminates these individual selection transistors entirely, using a different architecture where unit cells are directly coupled to selection lines through local block selectors, thereby reducing area while maintaining selection capability

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent merges the selection function from individual unit cell level to a higher level using local block selectors that control multiple unit cells simultaneously. Multiple unit cells share common selection lines and are grouped into local blocks, combining their selection control into fewer, larger-scale selection elements rather than having separate control for each cell

Inventive Principle:

Principle #5Merging (Combining)

2Area of stationary object

If the array area is reduced by eliminating selection transistors, then the density is improved, but the complexity of selection control increases

Engineering Contradiction:

ImproveEPROM cell array areaVSAvoidselection control complexity

Core Design Contradiction:

Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent segments the cell array into multiple local blocks, where each local block is independently controllable through local block selectors. This segmentation allows the large array to be divided into manageable sections, reducing the complexity of selecting individual cells while maintaining overall array functionality and enabling hierarchical control

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS9916898B2EPROM cell array, method of operating the same, and memory device including the same

AI summary

A memory cell array includes local blocks disposed in parallel with rows and arrayed along a direction parallel with columns, first selection lines being parallel with the rows and including a couple of first selection lines connected to each of the local blocks, second selection lines disposed in parallel with the columns, and local block selectors disposed between the plurality of local blocks. Each of the local block selectors is disposed between a Qth wherein, “Q” is an odd number local block and a (Q+1)th local block among the local blocks to electrically connect unit cells disposed in any one of the Qth local block and the (Q+1)th local block to the second selection lines. The unit cells in the local blocks are disposed at cross points of the first selection lines and the second selection lines, respectively. Each of the unit cells includes a P-channel MOSFET.