EPROM Cell Array Without Selection Transistors

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing EPROM cell arrays require a large area due to the need for a selection transistor for each unit cell, which increases the overall size and complexity of the memory device.

Innovation Solution

The EPROM cell array operates without a selection transistor by using common first and second selection lines to selectively program and read unit cells, reducing the area required for each unit cell and improving redundancy characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If a selection transistor is used for each unit cell, then the ability to selectively program and read unit cells is improved, but the area of the EPROM cell array increases

Engineering Contradiction:
Improveselectability of unit cellsVSAvoidarea of EPROM cell array
Core Design Contradiction:
Ease of operationVSArea of stationary object

Solution Approach 1:

The patent merges the selection functionality for multiple unit cells into shared selection lines. Instead of having dedicated selection transistors for each unit cell, the invention uses common first selection lines connected to drains of unit cells in the same row and common second selection lines connected to sources of unit cells in the same column, allowing multiple unit cells to be selected simultaneously through line intersections.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The selection lines serve multiple functions: they act as both row and column selectors, and can be used for both programming and reading operations. The first selection lines are coupled to drains of unit cells disposed on the same row, while the second selection lines are coupled to sources of unit cells disposed on the same column, creating a universal selection mechanism.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Area of stationary object

If selection transistors are removed from each unit cell, then the area of the EPROM cell array is reduced, but the complexity of the selection mechanism increases

Engineering Contradiction:
Improvearea of EPROM cell arrayVSAvoidcomplexity of selection mechanism
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The selection mechanism is segmented into two independent sets of selection lines: first selection lines connected to drains and second selection lines connected to sources. This segmentation allows the selection function to be distributed across multiple simpler components rather than concentrated in complex per-cell transistors.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces intermediary selection lines that mediate between the control logic and the unit cells. The first and second selection lines act as intermediaries that carry selection signals across rows and columns, simplifying the direct control structure while maintaining selection capability.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for efficient programming and reading of unit cells without the need for selection transistors, reducing the overall area of the EPROM cell array and enhancing redundancy, thereby improving memory device performance and efficiency.

Implementation Method 1

The FET has a floating gate disposed over the channel. Information may be stored as a charge that is injected into the floating gate, which is electrically isolated. The charge remains in the floating gate even though power supply is switched off because it is electrically isolated.

Methodology Applied
Scientific EffectElectrostatic charge storage: Capacitance

Implementation Method 2

The charge of the floating gate exerts influence on the conductivity of the channel between the source and the drain. Therefore, by detecting current flowing through the channel, information may be read from the FET device.

Methodology Applied
Scientific EffectElectrostatic field effect: Electric Field

Data Source

PatentUS9355726B2EPROM cell array, method of operating the same, and memory device including the same
Publication Date: 2016.05.31 SK HYNIX INC
  • US9355726B2 patent drawing
  • US9355726B2 patent drawing
  • US9355726B2 patent drawing

AI summary

An EPROM cell array includes a cell array including multiple unit cells, each of which includes a MOSFET having a floating gate, and which are disposed in an array with a plurality of rows and a plurality of columns; multiple first selection lines each coupled with drains of unit cells, which are disposed on the same row among the multiple unit cells; and multiple second selection lines each coupled with sources of unit cells, which are disposed on the same column among the unit cells, wherein a selected unit cell to be programmed or read is selected by one of the multiple first selection lines, and one of the multiple second selection lines.