EPROM Cell Double-Layer Floating Gate Metal Interconnects
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Solution Overview
Problem
Conventional PROM and NMOS chips face issues with fuse reliability and complexity in programming, particularly in inkjet printheads, where fuses can damage the orifice layer and cause printing defects, and EPROM cells require additional layers increasing cost and complexity.
Innovation Solution
Adapting EPROM technology to use existing layers in PROM chips by creating capacitive coupling between metal layers to form a floating and control gate structure, eliminating the need for additional process steps and layers, allowing for programmable read-only memory functionality without the drawbacks of fuses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If fuses are used in PROM chips for programming, then individual bit addressing is achieved, but reliability deteriorates due to fuse damage and debris causing printing defects
Solution Approach 1:
The patent extracts the problematic fuse element from the circuit and replaces it with an EPROM cell that uses non-destructive programming. The fuse is completely removed and replaced by a transistor-based cell with floating gate and control gate structures that can be programmed without physical damage to circuit elements.
Solution Approach 2:
The patent replaces the disposable fuse (which must be burned out and cannot be reused) with an EPROM cell that can be programmed repeatedly without degradation. The EPROM cell maintains its functionality after programming, allowing for rework and repair capabilities that fuses lack.
2Reliability
If EPROM cells with two gates are implemented, then fuse reliability is improved, but device complexity increases due to additional layers
Solution Approach 1:
The patent makes the existing metal layers serve dual purposes: they function as both interconnect wiring and as the gate structures for the EPROM cells. The first metal layer becomes the floating gate and the second metal layer becomes the control gate, eliminating the need for separate gate layers while maintaining EPROM functionality.
Solution Approach 2:
The patent merges the interconnect function with the gate function by using the existing metal layers for both purposes. This consolidation eliminates the need for additional process layers that would normally be required for EPROM structures, reducing device complexity while maintaining reliability.
3Reliability
If additional layers are added for EPROM functionality, then programming reliability is improved, but manufacturing cost increases
Solution Approach 1:
The patent enables existing metal layers to serve multiple functions as both interconnects and EPROM gates, eliminating the need for additional manufacturing layers and associated process steps, thereby reducing manufacturing cost while maintaining EPROM programming capability.
Solution Approach 2:
The patent allows the existing chip structure to serve its own dual purpose by using the metal interconnect layers as the gate structures for EPROM cells, eliminating the need for separate gate fabrication processes and reducing overall manufacturing complexity and cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables reliable and cost-effective implementation of EPROM functionality in existing chip structures, reducing complexity and maintaining performance while avoiding the limitations of fuses, with EPROM cells capable of holding charge for extended periods and supporting cumulative data storage.
Implementation Method 1
a control gate, comprising a second metal layer, capacitively coupled to the first metal layer via a second dielectric material disposed therebetween
Implementation Method 2
separated from the semiconductor substrate by a first dielectric layer
Implementation Method 3
These negatively charged electrons act as a barrier between the control gate and the floating gate
Data Source
Figure 1A~2
Figure 3~5
Figure 6
AI summary
An EPROM cell (70) includes a semiconductor substrate (52), having source and drain regions (76, 74), a floating gate (72), including a semiconductive polysilicon layer (56) electrically interconnected with a first metal layer (60), and a control gate (64), including a second metal layer. The floating gate (72) is disposed adjacent to the source (76) and drain (74) regions and separated from the semiconductor substrate (52) by a first dielectric layer (54), and the second metal layer (64) of the control gate is capacitively coupled to the first metal layer (60) with a second dielectric layer (62) therebetween. A resistor (78) couples the control gate to the drain region to limit the breakdown current of the EPROM cell.