EPROM Cell With Dual Gate Oxide Thicknesses
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Solution Overview
Problem
Integrated circuit designs face challenges in maintaining ten-year data retention for electrically programmable read-only memory (EPROM) cells with thinner tunnel oxide layers, as the reduced thickness leads to faster electron discharge and increased complexity in ensuring data integrity.
Innovation Solution
A system and method utilizing an n-channel metal oxide semiconductor (NMOS) select transistor with a 60 Å gate oxide layer and a p-channel metal oxide semiconductor (PMOS) breakdown transistor with a 20 Å gate oxide layer, where a programming voltage pulse is applied to break down the PMOS transistor's gate oxide without damaging the NMOS transistor, ensuring infinite data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the tunnel oxide thickness is reduced to 60 Å to enable scaling, then device dimensions are reduced, but data retention capability deteriorates due to faster electron discharge
Solution Approach 1:
The patent divides the memory cell into two separate transistors: an NMOS transistor with 60 Å gate oxide for select/control functions and a PMOS transistor with 20 Å gate oxide for breakdown-based data storage. This segmentation allows each transistor to be optimized for its specific function, with the thin-oxide PMOS providing reliable data retention through breakdown while the thicker-oxide NMOS handles switching operations.
Solution Approach 2:
The patent applies different gate oxide thicknesses to different transistors within the same memory cell based on their specific functional requirements. The PMOS transistor uses 20 Å gate oxide where breakdown characteristics are needed for data storage, while the NMOS transistor uses 60 Å gate oxide where standard switching performance is required. This local differentiation resolves the contradiction between scaling and data retention.
2Ease of manufacture
If the tunnel oxide thickness is reduced to 60 Å to reduce manufacturing complexity, then fabrication steps are simplified, but electron isolation capability deteriorates leading to faster discharge
Solution Approach 1:
The patent implements local quality by assigning different gate oxide thicknesses to different transistors based on their functional roles. The PMOS transistor with 20 Å gate oxide provides the necessary electron isolation for data storage through its breakdown characteristics, while the NMOS transistor with 60 Å gate oxide handles control functions. This resolves the contradiction by optimizing each component locally rather than applying a uniform thickness.
Solution Approach 2:
The patent converts the harmful effect of thin oxide (increased electron discharge) into a beneficial feature by utilizing the breakdown characteristics of the 20 Å PMOS gate oxide. The controlled breakdown creates a permanent conductive path that serves as the stored data state, transforming what would normally be a reliability issue into the fundamental storage mechanism.
3Device complexity
If a uniform 60 Å gate oxide is used in both transistors to simplify design, then design complexity is reduced, but programming current requirements increase and disturb issues arise
Solution Approach 1:
The patent segments the transistor design into two types with different gate oxide thicknesses optimized for their specific functions. The PMOS with 20 Å oxide is designed specifically for breakdown-based programming with lower current requirements, while the NMOS with 60 Å oxide handles select operations. This segmentation eliminates the need for high programming currents that would cause disturb issues in a uniform design.
Solution Approach 2:
The patent changes the gate oxide thickness parameter from a uniform 60 Å to differentiated values (20 Å for PMOS, 60 Å for NMOS) based on functional requirements. This parameter change enables the PMOS to undergo controlled breakdown at lower programming currents, reducing both energy consumption and the risk of disturb effects in adjacent cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a low-cost, reliable method for achieving ten-year data retention with significantly lower programming currents, eliminating 'read disturb' and 'program disturb' issues, and maintaining data integrity across various temperatures.
Implementation Method 1
a programming voltage pulse is applied to break down the PMOS transistor's gate oxide
Implementation Method 2
hot electrons are generated by impact ionization in a channel
Implementation Method 3
some of the channel hot electrons are injected through a tunnel oxide to a polysilicon floating gate
Data Source
AI summary
A system and method are disclosed for providing an electrically programmable read only memory (EPROM) in which each memory cell comprises an NMOS select transistor with a thick gate oxide and a PMOS breakdown transistor with a thin gate oxide. The source of the NMOS transistor and the source, drain and N well of the PMOS transistor are connected. The gate of the PMOS transistor is grounded. Under the control of the NMOS transistor, a programming voltage pulse is passed to the N well of the PMOS transistor of a selected memory cell. The magnitude of the voltage is sufficient to break the thin gate oxide of the PMOS transistor without damaging the NMOS transistor. Because the memory state of the memory cell depends on the breakdown status of the PMOS transistor, the data may be retained in the memory cell for an unlimited period of time.