EPROM Cell Modified Floating Gate Structure

Solution Overview

Problem

Inkjet printing technologies, such as thermal inkjet (TIJ) devices, face challenges in reducing the size of EPROM cells to increase packing density and prevent unauthorized cloning, while maintaining performance and security.

Innovation Solution

The use of a floating-gate transistor with a modified gate structure and a reduced surface area for the first metal layer, combined with short-channeled gate designs for select transistors, allows for smaller EPROM cell size, increased packing density, and enhanced program ratio, while functional and process tuning compensates for reduced coupling and program ratios.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If the surface area of the first metal layer is reduced, then the EPROM cell size is reduced and packing density is increased, but the coupling ratio and program ratio are reduced

Engineering Contradiction:

ImproveEPROM cell sizeVSAvoidcoupling ratio

Core Design Contradiction:

Area of moving objectVSReliability

Solution Approach 1:

The patent applies local quality by creating an asymmetric gate structure where the first metal layer has a reduced surface area compared to conventional designs. This localized modification in the gate region allows smaller cell size while the rest of the transistor structure maintains normal dimensions to preserve electrical performance. The selective reduction of metal layer area in specific locations achieves area reduction without proportionally reducing coupling ratio.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent changes physical parameters by reducing the surface area parameter of the first metal layer while adjusting other parameters such as the channel length and gate oxide thickness to compensate. By modifying the channel length to be shorter and adjusting the gate structure dimensions, the patent achieves a new parameter balance that reduces cell area while maintaining acceptable coupling ratio through optimized parameter combinations rather than uniform scaling.

Inventive Principle:

Principle #35Parameter changes

2Area of moving object

If the surface area of the first metal layer is reduced, then the EPROM cell size is reduced and packing density is increased, but the program ratio is reduced

Engineering Contradiction:

ImproveEPROM cell sizeVSAvoidprogram ratio

Core Design Contradiction:

Area of moving objectVSManufacturing precision

Solution Approach 1:

The patent applies local quality by creating an asymmetric gate structure where the first metal layer has a reduced surface area compared to conventional designs. This localized modification in the gate region allows smaller cell size while the rest of the transistor structure maintains normal dimensions to preserve electrical performance. The selective reduction of metal layer area in specific locations achieves area reduction without proportionally reducing coupling ratio.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent changes physical parameters by reducing the surface area parameter of the first metal layer while adjusting other parameters such as the channel length and gate oxide thickness to compensate. By modifying the channel length to be shorter and adjusting the gate structure dimensions, the patent achieves a new parameter balance that reduces cell area while maintaining acceptable coupling ratio through optimized parameter combinations rather than uniform scaling.

Inventive Principle:

Principle #35Parameter changes

3Area of moving object

If short-channeled gate designs are used for select transistors, then EPROM cell size is reduced and packing density is increased, but manufacturing complexity increases

Engineering Contradiction:

ImproveEPROM cell sizeVSAvoidmanufacturing complexity

Core Design Contradiction:

Area of moving objectVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the transistor gate into distinct segments - the first metal layer with reduced surface area and the polysilicon layer. This segmentation allows independent optimization of each layer's dimensions and properties. The short-channeled gate is implemented as a separate structural element with defined boundaries, allowing precise control over channel length while maintaining manufacturing feasibility through clear fabrication process steps for creating segmented structures.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS9953991B2EPROM cell with modified floating gate

Publication Date: 2018.04.24 HEWLETT PACKARD DEVELOPMENT COMPANY LP

AI summary

An electronically programmable read-only memory (EPROM) cell includes a semiconductor substrate having source and drain regions; a floating gate, adjacent to the source and drain regions and separated from the semiconductor substrate by a first dielectric layer, the floating gate including: a polysilicon layer formed over the first dielectric layer; a first metal layer electrically connected to the polysilicon layer, where the surface area of the first metal layer is less than 1000 μm2; and a control gate comprising a second metal layer, capacitively coupled to the first metal layer through a second dielectric material disposed therebetween.