Embedded Package Substrate Capacitor Lateral Electrode Extension
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Solution Overview
Problem
Conventional embedded package substrate (EPS) capacitors face limitations in reducing parasitic inductance and resistance, and enhancing routing flexibility due to limited via placement and increased current density, which affects their performance in high-frequency regimes.
Innovation Solution
The package substrate design includes laterally extending metal plates from the capacitor electrodes, allowing for increased via placement and reduced current density, thereby reducing parasitic inductance and resistance, and providing enhanced routing flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vias are placed to connect capacitor electrodes to metal layers, then electrical connections are established, but parasitic inductance and resistance increase due to limited via placement and high current density
Solution Approach 1:
The patent extends the capacitor electrodes laterally in the planar direction to form enlarged electrode structures. This dimensional extension allows multiple vias to be distributed across a larger area, reducing current density through each via and thereby reducing parasitic inductance and resistance while maintaining reliable electrical connections.
2Object-generated harmful factors
If decoupling capacitor is integrated into the die, then parasitic inductance and resistance are minimized, but die real estate cost increases significantly
Solution Approach 1:
The patent embeds the decoupling capacitor within the package substrate structure, nesting it between metal layers and utilizing the substrate's internal volume. This approach achieves low parasitic inductance and resistance similar to die integration while avoiding the high cost of occupying valuable die real estate, as the capacitor is housed in the substrate rather than the expensive semiconductor die.
3Ease of manufacture
If decoupling capacitor is mounted on the circuit board, then manufacturing cost is reduced, but separation distance from die increases causing high parasitic inductance and resistance
Solution Approach 1:
The patent transitions the capacitor placement from the traditional board-level (2D plane) to within-substrate embedding (3D internal structure). By placing the capacitor inside the package substrate and extending electrodes laterally, the design achieves proximity to the die without requiring board-level mounting, thus maintaining low parasitic values while keeping manufacturing costs lower than die integration.
4Ease of manufacture
If via footprints are limited to capacitor electrode areas, then manufacturing is simplified, but routing flexibility in metal layers is reduced
Solution Approach 1:
The patent laterally extends the capacitor electrodes to create enlarged electrode structures that provide expanded footprints for via placement. This dimensional extension decouples via locations from the constraints of the original small electrode areas, enabling greater routing flexibility in metal layers while maintaining manufacturing simplicity through the extended electrode geometry.
Data Source
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AI summary
A package substrate is provided that includes a core substrate and a capacitor embedded in the core substrate including a first side. The capacitor includes a first electrode and a second electrode disposed at opposite ends of the capacitor. The package also includes a first power supply metal plate extending laterally in the core substrate. The first power supply metal plate is disposed directly on the first electrode of the capacitor from the first side of the core substrate. A first via extending perpendicular to the first metal plate and connected to the first power supply metal plate from the first side of the core substrate.