Extended Page Table Memory Virtualization

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Solution Overview

Problem

Virtualization systems face complexity and performance overhead in managing memory for guest software executing on multiple virtual machines sharing a host machine, particularly due to the need for remapping and protecting physical memory, which is not directly compatible with the guest-physical memory abstraction.

Innovation Solution

The implementation of an Extended Page Table (EPT) mechanism by the Virtual Machine Monitor (VMM) to translate and protect guest-physical addresses to host-physical addresses, enabling efficient memory management and virtualization of physical memory through EPT controls and tables.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the VMM directly manages physical memory for multiple virtual machines, then memory protection and virtualization are achieved, but performance overhead and system complexity increase

Engineering Contradiction:

Improvememory protectionVSAvoidperformance overhead

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent introduces an Extended Page Table (EPT) as an intermediary data structure between guest physical addresses and host physical addresses. The EPT mechanism acts as a mediator that automatically performs address translation and protection checks, eliminating the need for the VMM to directly manage each memory access. This reduces performance overhead while maintaining memory protection through hardware-supported EPT entries that map guest physical addresses to host physical addresses.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent replaces the software-based memory management mechanism (VMM directly handling page table translations) with a hardware-supported mechanism (EPT in the memory management unit). By substituting the mechanical software intervention with hardware-supported EPT translation, the system achieves faster address translation and reduced VMM involvement, thereby improving performance while maintaining protection.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Adaptability or versatility

If the VMM implements comprehensive memory management for guest virtual machines, then memory virtualization and protection are achieved, but system complexity increases

Engineering Contradiction:

Improvememory virtualizationVSAvoidsystem complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments the memory management functionality into distinct components: guest virtual addresses are translated to guest physical addresses by the guest OS, and then guest physical addresses are translated to host physical addresses by the EPT mechanism. This segmentation separates concerns between the guest OS and the VMM, reducing system complexity by allowing each component to handle only its specific translation task rather than managing the entire address translation chain.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The EPT mechanism enables the memory management system to serve itself by automatically translating guest physical addresses to host physical addresses without requiring VMM intervention. The hardware-supported EPT translation operates autonomously, reducing the complexity of VMM implementation while maintaining full memory virtualization capabilities.

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS8645665B1Virtualizing physical memory in a virtual machine system utilizing multilevel translation table base registers to map guest virtual addresses to guest physical addresses then to host physical addresses

Publication Date: 2014.02.04 INTEL CORP

AI summary

A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.