EPT Switching for Secure Inter-Processor Instruction Sending
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current virtualization technologies experience significant performance degradation due to the need for VM Exit and VM Entry when sending sensitive instructions like Inter-Processor Interrupts, which can be exploited by attackers, leading to performance losses in multiprocessor systems.
Innovation Solution
An instruction sending method that switches an extended page table (EPT) from a first EPT to a second EPT, allowing the processor to execute target instructions without relying on virtual machine monitors, thereby isolating the processor from potential attacker-controlled code and avoiding performance-hitting VM transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the Hypervisor intercepts and executes sensitive instructions through VM Exit and VM Entry, then system security is improved, but performance is greatly degraded
Solution Approach 1:
The patent segments the instruction execution process into two independent EPTs (first EPT for normal instructions, second EPT for sensitive instructions). By dividing the page table structure, the system can selectively apply different execution paths: normal instructions execute directly in the virtual machine, while sensitive instructions trigger EPT switching to the second EPT for Hypervisor-controlled execution, thereby maintaining both performance and security without requiring full VM Exit/Entry overhead for all instructions
Solution Approach 2:
The patent introduces EPT switching as an intermediary mechanism between the virtual machine and Hypervisor. Instead of directly using VM Exit/Entry for all sensitive operations, the system uses EPT table switching as a mediator that allows the virtual machine to retain control for normal operations while seamlessly transitioning to Hypervisor control only when sensitive instructions are detected, reducing the frequency and overhead of control transitions
2Reliability
If the virtual machine runs in non-root mode with Hypervisor interception, then security control is improved, but performance loss increases due to frequent VM Exit and VM Entry
Solution Approach 1:
The patent prepares two EPTs (first EPT and second EPT) in advance before the virtual machine needs to execute sensitive instructions. The first EPT is configured for normal instruction execution with direct virtual machine control, while the second EPT is pre-configured for sensitive instruction execution with Hypervisor control. This preliminary preparation eliminates the need for time-consuming EPT construction during instruction execution, reducing transition overhead
Solution Approach 2:
The patent makes the EPT configuration dynamic by allowing switching between the first EPT and second EPT based on the instruction type. The system dynamically adjusts the EPT selection at runtime: using the first EPT for normal instructions to maximize performance, and switching to the second EPT only when sensitive instructions are detected. This dynamic adaptation minimizes the time spent in security-checking modes while maintaining security control
Data Source
AI summary
An embodiment of the present disclosure provides an instruction sending method and apparatus and relates to the technical field of computers. The method includes: switching an extended page table (EPT) from a first EPT to a second EPT, in response to an instruction sending request for sending a target instruction to a second processor; obtaining a target code according to the second EPT, the target code being a code related to sending the target instruction; executing the target code, to make the first processor sends the target instruction to the second processor. The embodiment of the present disclosure is used to avoid an inter-processor instruction from being utilized by an attacker, and meanwhile, avoid performance of a virtual machine from being greatly influenced when an instruction is sent.