Determining Successive Equal Bits in High-Speed Bit Streams

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Solution Overview

Problem

Current methods for analyzing data-dependent jitter in high-speed digital interfaces are limited by the inability to timestamp all transitions due to time measurement constraints, making it difficult to determine the number of successive equal bits preceding an edge within a bit stream, especially for unknown repetitive bit sequences.

Innovation Solution

An apparatus that determines a preset number of edges coprime to the repetitive bit sequence, allowing for non-uniform time stamping of edges, which enables the determination of successive equal bits and reconstruction of the bit sequence without the need for additional hardware or complex spectral jitter decomposition.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If time stamping is performed on all transitions in a high-speed bit stream, then complete bit history information is obtained, but the measurement system cannot keep up with data rates above 100 Msa/s versus 2.5 Gb/s interface speeds

Engineering Contradiction:
Improvebit history information completenessVSAvoidtime stamping speed
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent segments the continuous bit stream analysis into discrete periodic intervals, analyzing only specific edges (e.g., every Nth edge) rather than attempting to capture all transitions. This segmentation allows the measurement system to operate within its speed limitations while still gathering sufficient data to determine run length information through periodic sampling and mathematical reconstruction of the bit history.

Inventive Principle:
Principle #1Segmentation

2Loss of information

If additional hardware is added to count bits before each transition, then run length information is obtained, but memory bandwidth requirements and hardware complexity double

Engineering Contradiction:
Improverun length informationVSAvoidhardware complexity
Core Design Contradiction:
Loss of informationVSDevice complexity

Solution Approach 1:

The patent extracts only the essential timing information (time stamps of selected edges) from the bit stream, removing the need for complex additional hardware counters. By taking out only the critical temporal data points and using mathematical relationships to derive run length information, the system avoids the hardware complexity and memory bandwidth requirements associated with traditional counting methods.

Inventive Principle:
Principle #2Taking out (Extraction)

3Loss of information

If two time-stamper are used to provide run-length information, then complete run length data is obtained, but hardware requirements and memory bandwidth requirements double

Engineering Contradiction:
Improverun length informationVSAvoidhardware quantity
Core Design Contradiction:
Loss of informationVSQuantity of substance

Solution Approach 1:

The patent makes a single time-stamper perform multiple functions by configuring it to selectively time stamp different edges based on a periodic selection criterion. Instead of requiring two separate time-stamper units, the same hardware resource is universally applied to capture timing information at multiple strategic points in the bit stream, thereby deriving complete run length information through intelligent sampling rather than redundant hardware.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9164726B2Apparatus for determining a number of successive equal bits preceding an edge within a bit stream and apparatus for reconstructing a repetitive bit sequence
Publication Date: 2015.10.20 ADVANTEST CORP
  • US9164726B2 patent drawing
  • US9164726B2 patent drawing
  • US9164726B2 patent drawing

AI summary

An apparatus for determining a number of successive equal bits preceding an edge within a bit stream including a repetitive bit sequence includes an edge number determiner, an edge selector, a time stamper and an equal bits determiner. The edge number determiner determines a preset number of edges. The preset number of edges is coprime to a number of edges of the repetitive bit sequence or coprime to a maximal number of edges of the repetitive bit sequence. The edge selector selects edges of the bit stream spaced apart from each other by the preset number of edges. Further, the time stamper determines a time stamp for each selected edge of the bit stream and the equal bits determiner determines the number of successive equal bits preceding the edge based on determined time stamps of selected edges.