I/O Buffer Offset Mitigation Using Equal-Input Voltage Calibration
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Solution Overview
Problem
Input or output buffer offsets in integrated circuit devices, such as NAND flash memory, lead to errors in setup and hold time requirements due to variabilities in fabrication and signal termination impedance, causing operational failures.
Innovation Solution
Applying specific voltage levels to the inputs of the I/O buffer until the desired logic level transition occurs, and using calibration logic and circuitry to adjust the buffer's current paths and resistances to mitigate offset, ensuring accurate signal transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a differential amplifier is used to condition signals in an I/O buffer, then signal conditioning capability is improved, but voltage offset due to fabrication variability and impedance imbalance degrades signal transition accuracy
Solution Approach 1:
The patent applies preliminary action by performing offset calibration before normal operation. The calibration circuit determines the actual offset voltage of the differential amplifier and stores this information for use during signal conditioning, thereby pre-compensating for the offset that would otherwise degrade transition accuracy
Solution Approach 2:
The patent changes the parameter of the differential amplifier by dynamically adjusting its offset voltage based on calibration data. The calibration circuit modifies the amplifier's operating parameters to compensate for fabrication variations and impedance imbalances, thereby maintaining accurate signal transitions despite the inherent offset
2Device complexity
If I/O buffer offset is not mitigated, then device complexity is reduced, but setup and hold time requirements are violated causing operational failures
Solution Approach 1:
The patent introduces an intermediary calibration circuit that mediates between the simple differential amplifier and the timing requirements. This calibration circuit determines offset values and provides compensation without requiring a complete redesign of the buffer architecture, thereby maintaining relative simplicity while ensuring timing compliance
Solution Approach 2:
The patent implements feedback by using the calibration circuit to measure the actual offset and then applying compensation based on this measured information. The system uses the determined offset values to adjust subsequent signal conditioning operations, creating a closed-loop approach that ensures setup and hold time requirements are met
Data Source
AI summary
Memory including an array of memory cells might include an input buffer having calibration circuitry, a first input, a second input, and an output; and calibration logic having an input selectively connected to the output of the input buffer and comprising an output connected to the calibration circuitry, wherein the calibration logic is configured to cause the memory to determine whether the input buffer exhibits offset while a particular voltage level is applied to the first and second inputs of the input buffer, and, in response to determining that the selected input buffer exhibits offset, apply an adjustment to the calibration circuitry while the particular voltage level is applied to the first and second inputs until a logic level of the output of the selected input buffer transitions.