Equal-Length Interconnection Lines for UIS Wafer Testing
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Solution Overview
Problem
Existing methods for unclamped inductive switching (UIS) tests on power devices can damage logical chips when performed on systems with both logical and power chips in a package, necessitating a way to conduct UIS tests on wafers without packaging, ensuring the power devices can withstand energy dissipation during avalanche breakdown without causing unnecessary damage.
Innovation Solution
A probe card with symmetrically connected contact elements to separate current input areas of a power device on a wafer, coupled to an interconnection node and ground contact, allowing for controlled UIS testing by ensuring equal electrical potential across all source areas, preventing hot spots and technological defects-induced failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If UIS test is performed on packaged systems with both logical and power chips, then power device reliability can be tested, but logical chips may be damaged
Solution Approach 1:
The invention separates the testing process by performing UIS tests on power devices at the wafer level before packaging, dividing the testing stages into pre-packaging wafer testing and post-packaging functional testing. This segmentation allows aggressive UIS testing of power devices without exposing logical chips to damaging conditions.
Solution Approach 2:
The invention performs UIS testing as a preliminary action during wafer fabrication before packaging. By conducting the stress test early in the manufacturing process on bare wafer power devices, the system identifies defective power devices before they are assembled with sensitive logical chips into final packages.
2Reliability
If traditional UIS test methods are used on wafers, then power devices can be tested for avalanche breakdown capability, but unequal electrical potential may cause hot spots and false failures
Solution Approach 1:
The invention implements equipotentiality by connecting all source areas to a common ground reference through equal-length interconnection lines. This ensures that during UIS testing, all current channels experience identical electrical potential conditions, eliminating hot spots caused by potential differences and preventing false test failures.
Solution Approach 2:
The invention applies local quality by providing each source area with individually controlled equal-length interconnection lines to the common ground node. This localized approach ensures that each current channel has identical electrical characteristics, creating uniform testing conditions across different locations on the wafer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables reliable UIS testing on wafers, avoiding damage to power devices without technological defects, ensuring only faulty components are identified, and maintaining the integrity of non-defective chips during the testing process.
Implementation Method 1
a first contact element coupled to the interconnection node via a first interconnection line having a definite length; and a second contact element coupled to the interconnection node via a second interconnection line having the same definite length as the first interconnection line
Implementation Method 2
a ground contact, an interconnection node directly connected to the ground contact
Data Source
AI summary
A probe card with a ground contact, a first contact element and a second contact element is provided. The first contact element is coupled to an interconnection node via a first interconnection line having a definite length and the second contact element is coupled to the interconnection node via a second interconnection line having the same definite length. The interconnection node is directly connected to the ground contact.