Equal Thickness Gate Spacers for CMOS Devices
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Solution Overview
Problem
In CMOS technologies, NFET and PFET devices have unequal spacer thicknesses, leading to degraded device performance, especially as gate pitch scales below 50 nm, where there's no room for optimization, and equal spacer thickness is required for reliability and maximum space for gate and source/drain formation.
Innovation Solution
A method is provided to form equal thickness gate spacers for PFET and NFET devices through a series of dielectric layer deposition, recessing, and etching processes using conformal atomic layer deposition (ALD) or directed self-assembly (DSA) layers, followed by nitride liner and inter-level dielectric deposition, allowing for the formation of high-k metal gates between epi growth regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If unequal spacer thickness is used for NFET and PFET devices, then manufacturing cost is reduced through shared processes, but device performance is degraded due to longer proximity to the channel in NFET
Solution Approach 1:
The patent applies local quality by forming different spacer thicknesses for NFET and PFET devices through selective masking and etching processes. Specifically, a first spacer is formed with a first thickness for NFET devices and a second spacer is formed with a second thickness for PFET devices, allowing each device type to have optimized local characteristics for its specific performance requirements while using a unified manufacturing process flow.
2Productivity
If gate pitch is scaled below 50 nm, then device density is increased, but spacer thickness optimization becomes impossible due to limited space
Solution Approach 1:
The patent applies parameter changes by precisely controlling the thickness parameters of spacers and the dimensions of pinching-off dielectric layers. By adjusting the thickness of the first and second spacers to be within specific ranges (e.g., 5-20 nm), and by controlling the etch depths to expose gate hard masks at specific positions, the invention enables continued spacer optimization even at scaled gate pitches below 50 nm, maintaining adaptability in high-density device configurations.
3Reliability
If minimum insulator thickness is used for reliability, then contact to gate breakdown is prevented, but space for gate and source/drain formation is reduced
Solution Approach 1:
The patent applies dimensionality change by transitioning from planar spacer formation to three-dimensional spacer structures with vertical pinching-off dielectric layers. The pinching-off dielectric layers extend vertically from the substrate surface to the gate structure, creating a three-dimensional configuration that provides reliable electrical isolation in the vertical dimension while minimizing the horizontal footprint, thus preserving space for gate and source/drain formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures equal spacer thickness for both NFET and PFET devices, improving device performance by maintaining reliability and optimizing space for gate and source/drain formation, even at scaled-down gate pitches.
Implementation Method 1
depositing a first conformal atomic layer deposition (ALD) layer or depositing a first directed self-assembly (DSA) layer adjacent gate masks of the PFET and NFET devices
Data Source
AI summary
A method is presented for forming equal thickness gate spacers for a CMOS (complementary metal oxide semiconductor) device, the method includes forming a PFET (p-type field effect transistor) device and an NFET (n-type field effect transistor) device each including gate masks formed over dummy gates, forming PFET epi growth regions between the dummy gates of the PFET device, forming NFET epi growth regions between the dummy gates of the NFET device, depositing a nitride liner and an oxide over the PFET and NFET epi growth regions, the nitride liner and oxide extending up to the gate masks, and removing the dummy gates and the gate masks to form HKMGs (high-k metal gates) between the PFET and NFET epi growth regions.