Equalization Circuit Layout With Gate-Layer Power Routing
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Solution Overview
Problem
The challenge of reducing the size of traces in trace layers within integrated circuits, particularly in sense amplification circuits, becomes increasingly difficult as transistor sizes shrink, making it hard to accommodate multiple traces in a limited area.
Innovation Solution
The proposed solution involves integrating a power supply line within the gate layer of the equalization circuit, allowing for the formation of transistor units with a semiconductor substrate, thereby reducing the number of traces needed and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistor sizes are reduced to increase integration density, then the number of transistors per area increases, but the size of traces becomes increasingly difficult to reduce and manufacturing a trace layer accommodating multiple traces within a limited area becomes increasingly difficult
Solution Approach 1:
The patent merges the power supply line with the gate layer structure, integrating what were previously separate components (power delivery and gate control) into a unified layer. This consolidation reduces the total number of distinct traces required in the circuit, directly addressing the manufacturing difficulty of accommodating multiple traces in limited areas while maintaining high integration density.
Solution Approach 2:
The gate layer is designed to serve dual functions: it provides both the gate control signal for transistor operation and the power supply connection. By making the gate layer multi-functional, the patent eliminates the need for separate dedicated power supply traces, thereby reducing trace complexity and improving ease of manufacture without sacrificing integration density.
2Adaptability or versatility
If multiple traces are accommodated within a limited area to maintain circuit functionality, then circuit completeness is maintained, but manufacturing complexity increases
Solution Approach 1:
By combining the power supply line into the gate layer, the patent reduces the total number of separate traces needed in the circuit. This merger maintains all necessary circuit functionalities (both control and power delivery) while simplifying the overall trace layer structure, thereby reducing device complexity without compromising adaptability.
3Area of stationary object
If trace size is reduced to fit more traces in limited area, then area utilization improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent extracts the power supply function from the traditional trace layer and relocates it to the gate layer. This extraction eliminates the need for separate power supply traces, thereby reducing the number of traces that need to be precisely controlled in size. Area utilization is maintained through efficient gate layer design, while manufacturing precision requirements are reduced by having fewer traces to manage.
Data Source
AI summary
An equalization circuit structure includes a semiconductor substrate including an equalization active region; a gate layer including a gate pattern and a power supply line, wherein the gate pattern is disposed on the equalization active region and configured for forming a transistor unit with the equalization active region, and the power supply line electrically connects the equalization active region with an external power supply and is configured for supplying power to the transistor unit.