Equalizer Combining Component Filter Outputs for Read Channel
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Solution Overview
Problem
Current disk-based storage devices face challenges in achieving high performance gains in signal processing while maintaining low implementation costs, particularly in equalization and decoding processes, due to the complexity and cost associated with multiple analog-to-digital converter (ADC) arrangements and noise predictive calibrator (NPCAL) implementations.
Innovation Solution
The use of an equalizer that combines outputs from multiple component filters to create a single equalized data signal, coupled with a detector and decoder for iterative decoding, and a multiplexer to train the equalizer using hard decision information, reduces signal paths and complexity while achieving performance gains similar to multiple ADC and NPCAL setups.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple ADCs and NPCALs are used to achieve high performance gains in signal processing, then detection and decoding performance is improved, but device complexity and implementation cost increase
Solution Approach 1:
The patent combines multiple component filters (DFIR filters) into a single equalizer that processes a single digital data signal. The equalizer integrates the functionality of multiple filters and NPCALs by using a unified structure with adjustable coefficients that adapt to different signal conditions, thereby achieving similar performance gains without requiring separate hardware for each filter and calibrator.
Solution Approach 2:
The equalizer is designed as a universal component that can perform multiple functions: it acts as both a DFIR filter and an NPCAL by adjusting its coefficients based on input signal characteristics. This multi-functional design eliminates the need for separate dedicated circuits for different signal processing tasks, reducing overall device complexity while maintaining performance.
2Measurement precision
If multiple ADCs and NPCALs are implemented to achieve performance gains, then signal processing quality is improved, but implementation cost increases
Solution Approach 1:
The patent merges multiple signal processing functions into a single equalizer circuit, reducing the number of required components. By combining the functionality of multiple ADCs, DFIR filters, and NPCALs into one unified structure, the implementation cost is reduced while maintaining signal processing quality through adaptive coefficient adjustment.
Solution Approach 2:
The equalizer achieves different signal processing qualities by changing its coefficients rather than requiring different hardware configurations. The coefficients are adjusted based on input signal characteristics, allowing the same physical circuit to adapt to various signal conditions and maintain high processing quality without additional cost.
3Device complexity
If a single equalizer combines outputs from multiple component filters, then device complexity is reduced, but signal processing performance may be compromised
Solution Approach 1:
The equalizer employs dynamic coefficient adjustment to maintain high detection and decoding performance. The coefficients are continuously adapted based on the characteristics of the input signal and feedback from the decoding process, allowing the single equalizer to dynamically optimize its performance across varying signal conditions without requiring multiple static filter configurations.
Solution Approach 2:
The system uses feedback from the decoder to the equalizer to refine coefficient adjustment. The decoder provides information about signal quality and errors, which the equalizer uses to adjust its coefficients in subsequent processing, thereby maintaining high detection and decoding performance despite using a simplified single-equalizer architecture.
Data Source
AI summary
An apparatus comprises read channel circuitry and associated signal processing circuitry. The signal processing circuitry comprises: an equalizer configured to combine an output of two or more component filters into a single equalized data signal; a detector with an input coupled to an output of the equalizer configured to determine a set of soft outputs, hard decision information and reliability indicators of the single equalized data signal; a decoder with an input coupled to an output of the decoder configured to perform an iterative decoding process using the set of soft outputs, hard decision information and reliability indicators to determine a decoded data signal; and a multiplexer with a first input coupled to an output of the decoder, a second input coupled to an output of the detector, and an output coupled to an input of the equalizer. The hard decision information is used to train the equalizer.