Equalizer Circuit Feedback Delay Reduction
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Solution Overview
Problem
Conventional floating-tap decision feedback equalizer circuits face delays and timing issues with feedback due to increased load on multiplexer circuits as the number of D latch circuits increases, affecting the operation speed and compensation signal timing.
Innovation Solution
Incorporating a logic circuit to control the selection operation of the multiplexer and coefficient supply to the DA conversion circuit, allowing for reduced delay by selecting the tap position with the highest compensation intensity and adjusting coefficients before actual communication, thereby reducing the overall delay and improving feedback timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of D latch circuits is increased to spread the compensation range, then the compensation capability is improved, but the load on the multiplexer circuit increases making the delay larger and the feedback timing becomes severe
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing optimal tap positions and coefficients in a lookup table during system initialization or training phase. During actual communication, the system simply retrieves pre-computed values rather than performing real-time calculations through multiple D latch circuits, thereby reducing feedback delay while maintaining compensation capability.
Solution Approach 2:
The patent extracts the critical function of compensation from the time-consuming multiplexer and D latch circuit chain, isolating it into a simplified lookup table mechanism. This extraction allows the system to maintain compensation range while eliminating the bottleneck caused by sequential signal passage through multiple latch circuits.
2Productivity
If the operation speed of the circuit is increased to improve productivity, then the processing capability is improved, but the timing of feedback of the compensation signal becomes severe
Solution Approach 1:
The patent substitutes the mechanical sequential processing mechanism (signal passing through multiple D latch circuits and multiplexers) with a direct lookup table retrieval mechanism. This substitution eliminates the cumulative delay inherent in sequential circuit operation, allowing high-speed operation while maintaining reliable feedback timing.
Solution Approach 2:
By pre-computing and storing optimal compensation parameters in lookup tables during system initialization, the patent eliminates the need for real-time calculation and sequential processing. This preliminary action enables the system to operate at high speeds while maintaining precise feedback timing, as the lookup table provides immediate access to required compensation values.
Data Source
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AI summary
An equalizer circuit includes: an addition circuit (101) configured to add an input signal and a compensation signal; a comparison circuit (102) configured to compare an output signal of the addition circuit; a plurality of first latch circuits (103) configured to hold an output signal of the comparison circuit, the number of the plurality of first latch circuits being smaller by one than the number of taps in the equalizer circuit; a selection circuit (104) configured to select and output one of output signals of the comparison circuit and the plurality of first latch circuits; a second latch circuit (105) configured to hold an output signal of the selection circuit; and a digital analog conversion circuit (106) configured to generate the compensation signal, based on an output signal of the second latch circuit, in which the output signal of the selection circuit is supplied to the digital analog conversion circuit via the second latch circuit to reduce a delay of the compensation signal and relax the timing of feedback to the addition circuit.