Equalizer Group Delay Compensation Circuit

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Solution Overview

Problem

Conventional equalizer circuits face signal distortion due to group delay, which is exacerbated by parasitic resistance and capacitance, limiting manufacturing process margins and affecting electric characteristics.

Innovation Solution

An equalizer circuit design incorporating a first low pass filter, a gain control circuit, and a group delay compensation circuit connected in parallel, with a second low pass filter, to modulate the gain of the transfer function and compensate for group delay, thereby reducing surface area on a semiconductor substrate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a transconductor and capacitor are added to compensate for parasitic resistance and capacitance, then group delay characteristics are improved, but the area occupied on the semiconductor substrate increases

Engineering Contradiction:
Improvegroup delay characteristicsVSAvoidsemiconductor substrate area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent combines the group delay compensation function and gain modulation function into a single integrated circuit structure. The transconductor's output is directly connected to one plate of the capacitor, merging what would traditionally be separate compensation and gain control stages into one compact unit, thereby reducing overall substrate area while maintaining both functions.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The capacitor in the patent serves dual purposes: it provides group delay compensation by counteracting parasitic effects, and simultaneously enables gain modulation when combined with the transconductor. This multi-functionality eliminates the need for separate components, reducing the total area required on the semiconductor substrate.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Manufacturing precision

If transconductance is matched with capacitor to reduce transfer function error, then manufacturing precision is improved, but process margins are limited and electric characteristics cannot be guaranteed

Engineering Contradiction:
Improvetransfer function errorVSAvoidelectric characteristics guarantee
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent employs a feedback mechanism where the capacitor is connected back to the transconductor's output, creating a closed-loop system. This feedback structure automatically compensates for variations in transconductance values caused by manufacturing tolerances, ensuring consistent transfer function performance without requiring precise matching and thereby maintaining process margins.

Inventive Principle:
Principle #23Feedback

3Reliability

If group delay compensation is implemented using conventional biquadratic filter structure, then signal distortion is reduced, but device complexity increases

Engineering Contradiction:
Improvesignal distortionVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the equalizer circuit into distinct functional blocks: a first low-pass filter for initial signal conditioning, a transconductor-capacitor combination for group delay compensation and gain modulation, and a second low-pass filter for final output conditioning. This segmentation allows each block to be optimized independently, reducing overall complexity compared to a monolithic biquadratic filter while achieving the same distortion reduction.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS7844651B2Equalizer, group delay compensation circuit for the equalizer and method of compensating for group delay in the equalizer
Publication Date: 2010.11.30 SAMSUNG ELECTRONICS CO LTD
  • US7844651B2 patent drawing
  • US7844651B2 patent drawing
  • US7844651B2 patent drawing

AI summary

An equalizer, group delay compensation circuit for the equalizer and method of compensating for group delay may improve group delay characteristics in the equalizer. The equalizer circuit may include a first low pass filter configured to filter a received input signal to output a filtered input signal, and a gain control circuit connected to an output terminal of the first low pass filter, and configured to modulate a gain of a transfer function for the equalizer. The equalizer may include a group delay compensation circuit connected to the output terminal of the first low pass filter and configured to compensate for a group delay of the input signal, and a second low pass filter connected to the output terminal of the first low pass filter.