Equalizer Circuit Segmentation for Parasitic Capacitance Reduction
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Solution Overview
Problem
Existing equalizers face challenges in achieving a wide variable gain range to effectively equalize communication signals across various wiring lengths in communication media like on-board wiring and cables, due to increased parasitic capacitance which leads to over-equalization and limited gain adjustment.
Innovation Solution
The design incorporates two differential pairs of bipolar transistors with zero point generation circuits having the same peak characteristics, connected in a configuration that reduces parasitic capacitance by dividing the circuit elements and adjusting resistance values, allowing for a wider variable gain range and improved frequency compensation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple equalizers with three zero point frequencies are connected on the same wiring to achieve wide frequency compensation, then the frequency compensation range is improved, but the parasitic capacitance on the connection wiring increases, which limits the variable gain range and causes over-equalization in short wiring scenarios
Solution Approach 1:
The patent divides the equalizer circuit into multiple independent differential pairs (first differential pair with first zero point generation circuit, second differential pair with second zero point generation circuit) instead of connecting multiple equalizers through shared wiring. Each differential pair operates independently with its own zero point generation circuit, eliminating the parasitic capacitance issues caused by shared connection wiring while maintaining wide frequency compensation capability through parallel operation of the differential pairs
2Reliability
If the lower limit gain of the equalizer is set to account for parasitic capacitance effects, then the parasitic capacitance impact is reduced, but the variable gain range decreases and high-frequency performance is compromised
Solution Approach 1:
By segmenting the equalizer into independent differential pairs, each with its own zero point generation circuit, the patent eliminates the need to set a higher lower limit gain to compensate for parasitic capacitance. Each differential pair can operate with optimal gain settings independent of others, maintaining both equalization accuracy and wide variable gain range including high-frequency performance
Data Source
AI summary
The equalizer has a first differential pair having a first transistor and a second transistor and a second differential pair having a third transistor and a fourth transistor. A first terminal of the first transistor and a first terminal of the third transistor are connected to each other, and a first terminal of the second transistor and a first terminal of the fourth transistor are connected to each other, so that the first differential pair and the second differential pair have common input terminals. Also, resistors are respectively connected to second terminals of the first, second, third, and fourth transistors, a first zero point generation circuit is connected between the second terminal of the first transistor and the second terminal of the second transistor, and a second zero point generation circuit is connected between the second terminal of the third transistor and the second terminal of the fourth transistor.